Asynchronous Design Tools?

KeggInKenny asks: "I have the opportunity to engage in a research project involving large-scale asynchronous logic circuits. After evaluating possible tools for hardware description, simulation and implementation, I'm finding there's very little targeted toward asynchronous logic. VHDL is little changed from the 1987 standard which is not nearly as suited for large designs as it's name would suggest, and Verilog is too synchronous (or at least it's too easy to fall into the 'synchronous assumption' trap because of Verilog's C-style structure). Specifically: we are designing a low-power microcontroller for portable (read battery-powered) devices, and hoping that through asynchronous logic, we can greatly reduce power consumption. I'd like to see what the hardware gurus from the Slashdot community have to suggest for VLSIC design focusing on asynchronous research. What tools did you use to design the chips, did you run into synthesization problems, and did you find yourselves focusing on many local clocks, as seems to be the current async trend, or true unclocked hardware?"

Comments

Re:Asynchronous logic and Verilog

[addaon]

"This signature is a secret message encrypted with a one-time-pad"

And they say those things are unbreakable? Got it! Standard xor, byte at a time... you thought we wouldn't catch you?

1d48 081e 0012 4913 0b13 061a 000c 531d 5357 0e52 180c 0d15 4503 4919 0d53 320d 4a34 4100 0a02 520d 1f54 060b 4c1b 0804 1b45 4154 7b45 785a 3a43 454a 1f17 1000