Slashdot Mirror
Asynchronous Design Tools?
KeggInKenny asks: "I have the opportunity to engage in a research project involving large-scale asynchronous logic circuits. After evaluating possible tools for hardware description, simulation and implementation, I'm finding there's very little targeted toward asynchronous logic. VHDL is little changed from the 1987 standard which is not nearly as suited for large designs as it's name would suggest, and Verilog is too synchronous (or at least it's too easy to fall into the 'synchronous assumption' trap because of Verilog's C-style structure). Specifically: we are designing a low-power microcontroller for portable (read battery-powered) devices, and hoping that through asynchronous logic, we can greatly reduce power consumption. I'd like to see what the hardware gurus from the Slashdot community have to suggest for VLSIC design focusing on asynchronous research. What tools did you use to design the chips, did you run into synthesization problems, and did you find yourselves focusing on many local clocks, as seems to be the current async trend, or true unclocked hardware?"
Talk to this guy, he's very up-and-coming (and a slash user too :)
Feel that power? That's mah MOUSING FINGER
What does it mean to you?
:) If the experts at Manchester ran into a problem somewhere, odds are good you will too. Second, make sure you completely buy into their sect's interpretation of async before you jump in. They aren't the only sect in town.
...), so personallly I would go a different route. You should read up on what the QDI folks are doing. They've built their own (in many areas proprietary) flow, but the tools they use are readily available so depending on the complexity of your project you might be able to cook up your own, similar flow with the same tools.
First off, I highly recommend you read some of the ASYNC proceedings. (ASYNC = Nth International Symposium on Asynchronous Circuits and Systems, for N=[1,8]) The best stuff in async tends to get published there. I think they've always published through IEEE, so you can go there, or just do some google searching.
There are no async design flows which you can just drop in to replace Cadence or whatever your current synchronous flow is. There is also a lot of literature (see ASYNC proceedings) on what async people have to do to get commercial synthesis tools to play nice at all. Cadence-style synthesis just isn't there. (Which could be seen as a good thing, depending on your view of the current ack-bassward synchronous flows...)
Your goal sounds close enough to the Manchester ARM work that their tools might work for you. First, read their papers on their ARM work; the devil is always in the details. (Publishing is like sales, you bury the ugly details in the fine print.
I'm academically descended from the QDI culture in SoCal (Caltech, USC, whatever their startup is called these days,
My last point is a word of warning. As much as I like async and would like to see it more widely adopted, you are taking a big plunge, and if this is anything more than a course project, a big risk. Paraphrasing what a man who is much smarter than I said at the last ASYNC: If you read between the lines in the ASYNC proceedings you will see that the async community is basically a small (order hundreds) group of generally very smart people who are highly motivated. As often as not, they get things done by being highly motivated smart people. As a community, we haven't really demonstrated that our techniques to date will work for anyone but highly motivated smart people in the async community.
Look before you leap.
Brian