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Design Philosophy of the IBM PowerPC 970
D.J. Hodge writes "Ars Technica has a very detailed article on the PowerPC 970 up that places the CPU in relation to other desktop CPU offerings, including the G4 and the P4. I think this gets at what IBM is doing: 'If the P4 takes a narrow and deep approach to performance and the G4e takes a wide and shallow approach, the 970's approach could be characterized as wide and deep. In other words, the 970 wants to have it both ways: an extremely wide execution core and a 16-stage (integer) pipeline that, while not as deep as the P4's, is nonetheless built for speed.'"
the PowerPC 970 sacrifices some execution units -- including the Power4's second processor core -- for 64-bit compatibility and the SIMD unit.
This implies that the Power4 is not 64 bit -- which is of course wrong.
I would say that the PowerPC 970 trades the second core and fancier interconnects of the Power4 for lower power, cost, and the SIMD unit.
The article points out that a comparison with the AMD chip would be appropriate, but it's not "out there" right now as a basis for comparison. Hannibal says he'll probably use the 970 as a reference when he gets hold of the Opteron and does his down-in-the-registers review of it.
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The other responses to your question have pretty much hit it dead-on. I just wanted to comment that the PowerPC has always been the little brother of the Power architecture used originally in the RS6000 ... and now in almost everything IBM makes - AS400, E9000, etc.
... because of this the migration of everything into one die for the PowerPC was amazing.
;)
The first generations (601, 603/604 and the ?aborted? 620) of the PowerPC line were scaled-back versions of the Power and Power2 architectures respectively [the original Power architecture was mounted on a 3x5 daughter card with 4-5 separate chips [I'll have to go looking for my tech papers] making-up the core
Additionally, IBM has tended to work-out new capabilities -- such as the move to 64-bit and dual cores -- on the larger scale Power architecture, before attempting to stuff it into the smaller PowerPC pacakge [besides, IBM has to keep something to distinguish its pricier iron from the OEMs.
Natty
Maybe the rain Isn't really to blame. So I'll remove the cause, But not the symptom!
Plus, the Power4 is really designed as a server/Big Iron chip - it's really 2 CPUs on 1 die - and that's just not what an iMac needs.
I love vegetarians - some of my favorite foods are vegetarians.
The reason that Apple won't use the Power4:
It is HUGE.
The picture at the top right shows the Power4 multichip module as used in the p690. Yes, it is the 5" square thing in the guys hand.
There are better pictures of the MCM itself, but I couldn't find the close-up showing just the MCM in someone's hand.
The large size (along with everything it entails: it uses 125W power, and supposedly costs about $3500 to manufacture) is one indication that IBM designed the Power4 for its big-iron. Nevermind that IBM does offer the Power4 (sans MCM) in some of their smaller servers.
The PowerPC970 is the equivalent processor tweaked for the desktop/low-end servers.
The power4 costs 4-5k per cpu. Obviously too expensive for desktop systems because of high end server features and very large caches in the chip that will offer no performance benefit to desktop apps. Only heavily threaded multitasking apps running in parrallel will see the performance improvments by a power4. A web server running servlets and databases are the examples I refer to as heavily threaded multitasking applications. Adobe photoshop will show little performance difference and may even run slower on a power4 vs a powerpc 970 due to the lack of simd instructions.
IBM did good with this processor and its leaps and bounds ahead of the g4. The main limitation of the g4 is the lack of ddr memory support. In ddr macs the chipset has to slow down memory access to the cpu to 133mhz speeds and it creates a very serious bottleneck. This alone is bottlneckintgthe processor down to half its potential in +1 ghz processors. Expect a %200-300 performance increase with these new processors.
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" OpenMP is a specification for a set of compiler directives, library routines, and environment variables that can be used to specify shared memory parallelism in Fortran and C/C++ programs." All that would have to be added to gcc are the "compiler directives", as the "library routines" and "environment variables" aren't directly a part of the compiler.
Now, openMP is good for programming extremely high-performance shared-memory applications, like scientific computation applications and stuff like that. It really sounds like overkill for a desktop environment where it's probably easier to program a multithreaded application with standard IPC mechanisms where communication is required. And really high-performance applications could also be programmed using MPI and a message passing communication scheme, which is far more widely used (compare the # of people who know about openmp versus those who know about mpi), probably wouldn't be much less efficient, and would quite likely scale much better than a shared memory implementation.
40 bit address bus. Not a 40 bit data bus. BIG difference there.
And the 40 bit address bus is most likely a pin packaging limitation. They did not see a need to bring those extra 24 address lines out to the chip package. Internally, it is 64 bit. Much like the venerable MC68000 was 24 bit externally, but 32 bit internally.
But seriously, in the life-span of THIS processor implementation - do you seriously see ANY desktop manufacturer even thinking about putting that much RAM in their CPUs?? Heck 1GB of RAM is not 'standard' yet. Extrapolating w/ Moore's Law, we'll be approaching 40bits in 8 years. Apple will undoubtedly have another chip before then!
If you truly need THAT much physical storage today, you'll need to shell out for a SERIOUSLY large server. IBM's high-end p690 currently maxes out at 256GB. The virtual address space is undoubtedly much higher.
Tom