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AMD's Fab 30 Revealed
Harkids writes "AnandTech posted a
sweet article about a recent trip to AMD's newest chip manufacturing plant,
Fab 30 in Dresden, Germany. The article is more than just a walk around the building;
it includes juicy details of AMD's microprocessor manufacturing process, innovations,
and even has some Hammer info in it. A good read if you are interested in CPUs
or simply what AMD has up their sleeve."
now maybe we'll see a chip at 1/2 intel clock speed but twice as fast!! (oh wait, they already have those)
i would put a joke about the fab 5, but i don't remember what the fab 5 is so fuck it.
That area flooded a few weeks ago, and I heard someone say that luckily the plant didn't get destroyed. (aparantly, a few inches of water are enough to render a silicon fab useless)
This makes me wonder how vulnerable the chipmakers are... One good fire, flood or earthquake and we're without cpu's?
Imagine the sabotage posibilities... (hey Intel, for 1M, I'll wipe out amd ?)
A lot of people have been worrying about the recent 'dumbification' of stories on Slashdot like exercise bike games, non-existant decisions and what lawyers can learn from manga! But Harkids and Michael rush to save the day with this gruesomely geeky stuff:
it includes juicy details of AMD's microprocessor manufacturing process
Yes! YES! JUICY DETAILS OF PROCESSOR MANUFACTURE! YES!!
Slashdot is SAVED!!
mogorific carpentry experiments
Direct link to the article on one single page and without ads
"There is one thing that's for sure; AMD has not done a very good job of telling the public exactly what they're capable of from a manufacturing standpoint. Intel has been talking about their manufacturing capabilities for quite some time now and has left the market with the impression that they are the only leader in the x86 manufacturing world. It is a shame because in reality, AMD has quite a few accomplishments of their own to talk about but it's just a matter of getting them to loosen up and let you all in."
It is nice of AMD not to scream about what they can do in their labs, but actually rely on their current products.
I once did a gig at someone who manufactured fab equipment, and we all had to take this 3-day safety course, even those of us just working in the server room. And mostly it was 3-days of "This is chemical [insert name here] and it will kill you in [insert time here]. The way you will horribly die is [insert pain here]. So be careful." They made it sound like the room was full of gas that would eat you alive like that stuff from The Rock.
Intel may have tried to make the guys in the bunny suits cute, but after learning some of the dangerous stuff they're around I came to respect them for sure.
"Where quality is like a dead stinking rat - you just can't miss it."
Intel recently scrapped plans to firebomb the AMD Fab30 plant. When reached for comment an Intel spokesman said "The war for the desktop processor market is mostly over." AMD has declined to comment.
I've had enough abrasive sigs. Kittens are cute and fuzzy.
check out the specs for the hammer line... P4 can't touch it.
The combination of the Fab and the Dresden Design Center (DDC) was said to require a $2.3 million investment, with close to $2M already spent...
At that price, any Tom Dick or Harriet could set one up!
Of course, the next sentence makes it clear they're talking BILLIONS, not millions:
and the remaining $300M due to be used by the end of 2003. For an advanced microprocessor fabrication facility like Fab 30 this is the going rate for start-up costs, which is a major part of the reason why there are only two big competitors in the desktop CPU market; with such high barriers to entry, it's very difficult to become a mass market competitor in the CPU business.
SCO, Microsoft, P2P, what's your hot button?
By any chance were the /. editors on this tour?
(BTW here's a tip: Click on "Print this article" to see the whole article at once, ad-free, without having to wait for 7 pages of ads to download.)
John, Paul, Ringo, George.. who are the other 26?
Trolling is a art,
FYI, Hardware Analysis has an article on the AMD Dresden plant. They were invited to an AMD Media Workshop there.
5 80/
http://www.hardwareanalysis.com/content/article/1
A bit short but they've got two pictures of the plant.
- hama -
Did you remember back in 1999 when RAM prices went up, up and away, in a marked that's normally in a steady decline? That was (mostly) an earthquake in Taiwan knocking out plants.
While the AMD fab is quite a bit away from the river, up in the hills, other natural or unnatural disasters could be pretty severe.
However, it's not like the marked would totally collapse, AMD may have one main plant, Intel has a couple, UMC or whatever AMDs partner was called has some and I'm sure there are more flash etc. plants that could be converted on a longer timescale.
Of course if you had coordinated gro... *stops* *pullls out his Men In Black-zapper and zaps any Al-Quida associates reading this*
Kjella
Live today, because you never know what tomorrow brings
I mean, seriously, folks. I've been out of the technology loop for a good half year now (and there's another half year on top of that where I was just coasting), and even I'm not slow enough to mod this one up. Sixteen thousand 48-bit registers? *Think* about it!
... pepperoni and copper interconnects.
And Dresden has been running for quite some time, producing tons of 30nm copper interconnect (y'all do remember copper, right?) chips.
Still, Tiger's post got modded up to 5, so I guess that it's a phenomenally successful troll. It just irks me. It's like having an article on Microsoft's Windows code and having a comment about Microsoft switching over to gcc modded up!
--
-JC
http://www.jc-news.com/
Grove: So, what do you want on your TombStone, Jerry?
Sanders: Ummm
Grove: Aye, [shouting] TOMBSTONE PIZZA, CRAIG!
... is that the Hammer is being mass produced and is actually going to ship!
There is nothing wrong with being gay. It's getting caught where the trouble lies.
I really wish apparently technical essays here were not scored by a god damned popularity contest ...
The PowerPC was designed to make it easy for M68K users to migrate to it, which is why companies like Apple and the remnents of Commodore are indeed/have indeed done exactly that. It has considerably more than the M68K's 16+internal registers, IIRC (it's been a long time since I looked at the specs, but one of the hallmarks of RISC design is to use the space that would have been devoted to complex instructions for more registers instead.)
16384x16 48 bit registers? I doubt anyone is going to come up with such a design any time soon. But simply having a different number of registers to an 80386 isn't entirely unlikely, even for a CPU with a legacy x86 compatability mode.
You are not alone. This is not normal. None of this is normal.
It seems to me that purchasing the Alpha would be a great deal for AMD. They are already in a position to design and manufacture it.
In addition, many still depend on the Alpha, and this would give AMD the server market it's always wanted, and has been trying to secure.
All this is not mentioning that the Alpha's perfomance has always been far better than x86. Just imagine what would happen if AMD came out with a 8GHz processor a year from now...
Just a little ranting from someone who does not want to see the Alpha go, and still remembers the potential they hold.
Slashdot gets worse every day... Pipedot: News for nerds, without the corporate slant
AMD's Fab 30, Simply Fabulous5 81/
http://www.hardwareanalysis.com/content/article/1
"I doubt anyone is going to come up with such a design any time soon. But simply having a different number of registers to an 80386 isn't entirely unlikely, even for a CPU with a legacy x86 compatability mode."
As an example of that in action, the AMD Hammer chips have an extra 16(?) general purpose registers accessible in x86-64 mode.
Back when Intel just released early 75Mhz and 100Mhz Pentiums, Alpha with their advanced CMOS process was pushing 600Mhz on RISC chips.
Nobody bought it.
Their sales people couldn't convince consumers that superior technology was worth the price. They generated no excitement! They hoped that the technology could speak for itself.
I've been told by a long time Alpha engineer that long time clients would call him directly asking about new products, bypassing the sales rep. At the same time Sun sales team was attacking like wolves and stole the high end server market.
The result is that Intel now owns most of Alpha technology including the engineering teams. The last Alpha EV7 system can do up to 256 MP, and 256GB RAM, all on high speed ultra-wide packet switched interconnect bus. HP has to play down its performance to justify moving to Itanium servers.
The first Itanium has problems with more than 4 MP. Thank you Mr. Capellas.
> the Hammer/x86-64 chips have ondie memory controllers AND more registers than i386++ type
:)
;)
> chips, combined they'll give a speed increase of not inconsiderable proportions.
It is notable to, er, note that the former advantage helps (possibly considerably) towards both recoded AND legacy (eg, normal) programs, whereas the additional physical registers would require recompilation in order to show a benefit, which means that everybody but Windows users will get an immediate use outta that.
Other advantages of the Hammer? Well, not counting the 64-bit yunk (that WILL provide benefits, but I want to cover benefits that will help legacy programs, like Civilization III, The Sims, Unreal II and other antiproductivity applications):
Hyper Transport. That's not much on its own, but it essentially equates to a reduction in loss of bandwidth to the chipset and between processors when you add an additional processor. On the Intel setups, the processors share a set amount of bandwidth to the chipset, so putting eight chips on a 2.4GB/s bus means that you have each chip getting 0.3GB/s. The AMD setup theoretically lets each processor get that 2.4GB/s. Of course, that's in a perfect world, chip-level, but it probably amounts to some benefit. AMD's K7 family has similar advantages, which probably assists in explaining why they get higher performance at each given clock in mainstream applications (which at least somewhat depend on the memory subsystem) even though the AMD cpu to memory bandwidth was usually 2.13GB/s (now it's 2.67GB/s, unless you count stuff like the nForce, which has some extra memory bandwidth, but the extra benefit there is eaten up by the onboard video), whereas the Intel cpu to memory bandwidth was usually 3.2GB/s. Anyway, the idea is that HyperTransport will (on a hypothetical level) make it much easier to make n-way systems without either a tremendous performance impact or an expensive crossbar workaround setup thingy.
SoI. Silicon-on-Insulator. This is one of those things that'll help with the process technology. In the end, it'll probably offer a little bit of a frequency boost by making the chip a little cooler or something like that. I forgot precisely what SoI's primary benefits were. It's been months since I've even thought about it.
Stages: As detailed here, the K8 adds two stages to the decoding part of the instruction pipe. The decoding part of the pipe is probably rather complex, so you may see a pretty neat frequency boost over the K7 family without the problem of a huge branch mispredict penalty. The number of cycles that a cpu wastes when it makes an incorrect guess on a low level "if/then" statement is somewhat proportionate to the number of pipeline stages. The AMD K6 and (iirc) Cyrix 6x86 were the mack daddies of branch prediction, since their pipes had only five stages or so, so they only had to wait a few cycles when they zigged instead of zagged. The PIII and K7 had over ten stages, so they had to wait a lot longer, but other advantages (such as the larger and sometimes faster caches and more accurate predictors) in those processors over their predecessors did their best to overcome this disadvantage. The Pentium 4 has a crippling 20 to 28 (depending on the situation, and depending how the trace cache handles the situation, and whether or not you want to count it) stages. This means that it can hit amazing clock frequencies, but it'll get cranky and drowsy for twice as long when it makes a predictive mistake. How does it get away with this? Well, the trace cache does its best to assist, but it didn't really help as much as I think the designers were hoping. But for multithreaded programs and OSes, the SMT implementation on the more recent members of the P4 family, an implementation known as "Hyper-Threading", probably pretty neatly alleviates much of this problem by putting operations from other threads into the cpu whenever the currently running thread stalls on a branch mispredict. The K8/Hammer approach is just to add stages where they hopefully will have the most balanced, beneficial effect to frequency boosting while only minimally increasing the branch penalty. SMT would be nice, but it isn't nearly as critical a need as it is on the P4.
Wider memory access. On the Sledge Hammer, if AMD's plans are still the same as when I wrote this, the memory controller (which is embedded onto the cpu) will access PC2700 memory in a 128-bit configuration (ignore the "126-bit" typo on the linked page -- I can't believe I didn't notice that when I typed it nearly a year ago!), which leads to a 5.3GB/s path to memory. That's damned good, though I really think AMD should have focused on 366/183MHz (equiv to "PC2933") or 400/200MHz (equiv to "PC3200") memory instead of the 333/166MHz PC2700 that came out over a year ago. Still, servers often use memory that's lower than bleeding edge clock in order to maintain reliability, so bleh. Still, 5.3GB/s isn't bad for a setup that isn't based on a shared bus.
Enhanced branch predictor. Well, that's if my notes from a year ago are accurate. If true, this'll probably overcome any mispredict penaly performance disadvantage from those abovementioned added stages.
Larger TLBs, TLB flush filter, etc.. This stuff will have itty bitty advantages on a per-clock performance basis, but every little bit helps.
Larger caches. Hey, I should look this up to see what they're planning on. Is it just 512KB on-die L2, or is AMD planning on bringing it up to 1MB L2? The interesting thing about AMD's designs is that the die is really small on each processor. Remember how AMD has gotten occasional fire for processors overheating? Well, aside from a stupid lack of shutdown diodes in the past, the real cause wasn't that the AMD processors used more heat than the Intel processors. They usually generated about the same amount of heat, often less, but their processor surface area was substantially smaller, which made the chips less expensive to produce and less likely to have defects. But when you try to push an equal amount of heat through half the surface area, you end up with a higher amount of heat per area, which equates to a higher running temperature. The funky thing about this is that you could just added a whopping huge amount of on-die cache. That'd increase performance while also increasing the surface area. But the heat production would not be substantially affected. So you'd end up with a lower temperature processor. So the Hammer will have a higher ratio of cache to processor units in the cpu, so it won't be as much of a fire hazard. Frankly, they should have put 1MB on-die L2 onto the Thoroughbred/AthlonXP.
Crap. I need to research more on the K8. It probably changed a lot since I went into hibernation. The interesting thing is that in the last half year, I've largely moved from being a Windows 2000 power user to a Linux coder (I still use both operating systems for several different purposes, but I'm talking primary usage). I stand to be in the group that benefits most from the Hammer when it comes out, since I'll be able to './configure && make' or 'qmake -project && qmake && make' most of the programs I use and/or develop. So I'll instantly see the benefit of those extra registers. ^_^
-JC
http://www.jc-news.com/