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AMD Moving to a 400MHz Bus?
An anonymous reader writes "According to this tantalizing Infoworld Scoop, AMD soon introduce a 400 Mhz bus. Seems that SiS's big announcement at CEBIT is the SiS748 chipset, which supports both 400 MHz DDR & AGP 8X, and is targeted at the upcoming Athlon 3200+."
There have been rumors about AMD going for a 400MHz bus for quite some time now. Some chipsets even have experimental support for it. With the Athlon 64 being delayed until September I would say that is the only way for AMD to try and stay competitive with the Barton core.
Maybe I'm being a little arrogant, but I still feel this isn't really much to be that excited about.
.: Max Romantschuk
Gee, good thing you know your metaphors, otherwise you'd be stirring a can of worms by leaving the wrong impression.
Stop by my site where I write about ERP systems & more
Hmm. Yes, the K7 has gone from 500MHz to 2250MHz over its lifespan so far - but Intel's P6 core went from 150Mhz PPro to 1400MHz PIII.
Looks to me like they could still have plenty of room to play.
Depending on what you use the PC for, you might not notice anything at all. Current desktop PCs are more than adequate for web/email/office work, and have been since Intel first hit 300 MHz or so. I have a PII 400 running Windows 2000 at work that does not seem slow at all running all the basic, standard applications.
If you do stuff that involves digital video, compiling source code, or other types of activities that actually push the CPU, you might notice a difference between a 266MHz system bus and a 333MHz system bus.
The speed of the front side bus determines in part how fast information can get to the CPU from main memory. If you have fast memory + a fast FSB, you can get your CPU to work pretty darn fast. Your main performance bottlenecks are still going to be memory latency and hard drive access speed, though.
But once information gets from there to the main system memory, if you can keep that CPU at high utilization, you'll notice a pretty significant boost in performance.
You see? You see? Your stupid minds! Stupid! Stupid!
AMD better forget these little incremental speed bumps and switch to a whole new architecture this year if they want to remain competetive.
It's called x86-64. The Opteron ships next month.
The current architecture is like milking a deadhorse and they are already running waay too hot.
I did not need that mental image...
Current Thoroughbred and Barton core Athlons don't run all that hot. An Athlon 3000+ runs cooler than a 3GHz P4.
I reclocked my TBred core Athlon XP 1700+ to 8x202MHz (404MHz DDR) on my ASUS A7N8X Deluxe motherboard (Corsair PC3200C2 DIMM). I kept the default core voltage (1.5v). MemTest86 verified that it works reliably. Upping the FSB is mostly a matter of motherboard and memory support, not CPU support (outside of being able to adjust the clock multiplier). A few years ago I reclocked a 150MHz Pentium to 1.5x100MHz. Worked just fine.
All digital data is synchronized to a clock, be it source-synchronous (i.e. clock comes with data), which is the case with DDR, or recovered clock (i.e. clock information is based on rate of change of incoming data). Whatever scheme you get, you will still have a clock inside at some point.
Traditionally, the memory elements or registers on a chip will ignore incoming data until the clock signal undergoes a positive transition, i.e. logic low to logic high. At that point, assuming the data has been stable for a long enough period of time before and after the clock edge, it will be captured. However, since there is only one positive edge per clock cycle, data can only be captured on that edge.
In a double-pumped scheme, what you have is a set of 2:1 multiplexors that go to two different sets of registers. One is sensitive to positive edges, the other is sensitive to negative edges, i.e. logic high to logic low transitions. If you simply wiggle the data out faster, and you have a double-pumped scheme with a small FIFO buffer, you can recover data twice as fast as a single edged scheme. On the interface itself, there are special low skew low insertion delay clock distribution schemes that enable this to happen without too many problems.
In a quad-pumped scheme, you actually have two separate clocks that are 90 degrees out of phase with each other. In effect, you have two positive and then two negative edges to work with internally now. You wiggle data out at 4x the single data rate, and have 4:1 multiplexers to the registers, plus (again) a careful layout of the internal clocks.
The area overhead in such schemes is minimal (~10% for DDR) and really takes advantage of the speed of on-chip devices. It does take some special consideration, but from the perspective of increased die size, it's not a problem. Power, however, is significantly increased for both I/O (SSTL-2 type stuff) and for core devices because of the data rates, and that is also a consideration during design of not only the power distribution, but also the package/module design and the board design.
And, FYI, Rambus uses multiple serial/deserialization (SERDES) that wiggles data between a pair of signals (positive and negative) whose voltage differential is recovered, not for individual levels, which (supposedly but not actually) simplifies matters. Transmitting data via this differential is actually much faster than a single-ended scheme like DDR currently is (single ended meaning all I/O refer to a common ground (and voltage reference)). Then they even IIRC get into exotic schemes like multi-level differential (i.e. steppings between 0 millivolts differential and full swing). I could be wrong about the latter though...