AMD Opteron Due In April

updog writes "Here's an article from Infoworld claiming that the new 64-bit AMD Opteron is ready to launch on April 22. Some of the notable features of the new chip are an address space capable of addressing up to 1 Terabyte of memory, the ability to link up to 8 processors without any external chips, and backwards compatibility with existing 32-bit applications ..." PapaFSmurf, meanwhile, links to a disclaimer-heavy article posted at amdboard.com which says that 64-bit Athlons may arrive in June rather than September as previously expected.

Comments

Not surprising

[rabtech]

Barton isn't enough to keep AMD going against Intel until Sept. Simply not gonna happen, and I think they have seen that coming and are trying to head it off by launching the Athlon64 closer to its originally planned release.

Once the Athlon64 is available and people are building systems using it, AMD just stole back the "King of PC processors" title and in a BIG way.

Re:Not surprising

[Loki_1929]

The nice thing about Opteron is that it's main competitor will be the P4 Xeon processor, which will soon start showing signs of age. The P4 was designed for high clock speeds, but it can only go so far. When Clawhammer is released this Winter, AMD will truly have a more rounded product line. For the time being, all they have is the Athlon, which seems like a big mistake to me.

AMD's future existence depends very much on the performance of the Opteron and Clawhammer with 32-bit applications, in a 32-bit environment. The best case scenario for AMD would be if M$'s next major OS release were 64-bit only. Unfortunately, this seems highly unlikely, but AMD can dream, can't they?

"Yes, sir, that new system with the latest Windows will be $12,000 if you go with Intel and the Itanium, or $699 if you go with AMD and the Athlon64. Yes, sir, it is pretty funny; I agree."

This is huge

[Toasty16]

Affordable x86 64-bit servers for the masses, this is going to revitalize AMD and really put it on the map as a serious challenger to Intel. I hope Chipzilla wakes up and sees that its incredibly expensive and backwards-incompatible Itanic 2 chips are the result of engineers developing for themselves instead of developing for the needs of their customers. Finally, AMD will be able to court the high profit business market, though I fear that they might alienate their hardcore enthusiast consumers in the process...

Re:wow

[No. 24601]

Actually, more people than you'd think. Most modern processors are limited to a 4 GB address space and one has to "hack" around this limitation to achieve larger spaces. The reason why I say more people than you'd think is that the 1 TB space would allow one to map any location on the largest hard drives available today to a virtual memory location. There would be a *tremendous* performance boost in doing this as opposed to other contemporary file management schemes.

Only 1 TB?

[MagPulse]

64 bits should give you 18 exabytes right? What's the limiting factor?

2^64 = 18,446,744,073,709,551,616
^EB ^PB ^TB ^GB ^MB ^KB

Re:Only 1 TB?

[cheezedawg]

The "limiting factor" was AMD's decision to only use 40 bit addresses at first.

32 compatibility mode vs. true 64 bit apps...

[mekkab]

Maybe I'm trying to open a can of worms similar to VI vs EMACS, but so be it.

More addressable memory: cool.
8 way processors: cool*. (insert "do you have parallel apps to take advantage?" disclaimer. And some apps do.)

But if all my stuff is running in some 32 bit compatibility mode, then what real gain am I going to realize? The article did mention something about faster registers- does that mean small fixed point instructions run faster? (like increment register i, or add n to x, etc.)

And how many apps for 64 bit exist in the market?
(I'm sure there are some grad students and some code breakers with some custom software, but that's not my aim...)

I guess what I'm asking is- aside from custom code, what are the reason for me to early adopt a 64bit architecture? Or should I just save my money for when things get cheaper?

Re:32 compatibility mode vs. true 64 bit apps...

[vlad_petric]

The width of the machine is not the number of threads it's able to run at a given time (SMT like P4), but the number of instructions you can execute in a cycle (in a parallel fashion, of course). The difference between x86 and Itanium is that on Itanium the instructions are "explicitly parallel", i.e. the compiler bundles instructions together and the processor knows it can execute them in parallel, while on x86 the processor is smarter and determines itself which
micro-ops (actually it's rops for AMD) it can execute in parallel.

You're very likely going to see speedups on 32 bit code, simply because Opteron is twice as wide as P4 (and this has nothing to do with the size of the operands, which probably is not going to matter as much).

As far as the 64 apps are concerned - Linux already runs on it.

Re:32 compatibility mode vs. true 64 bit apps...

[Anonymous Coward]

Actually, so does Intel, at this point. They have a hardwired instruction decode for the few operations that are used enough, or are 'important' enough to do so; then the rest of the instructions (which aren't hardwired in) are taken care of in microcode. Microcode essentially does conversion of the 'CISC' instruction to a series of 'RISC' instructions; although when it comes down to it, it's really quite rare to find a pure RISC design anymore; People quickly point to the PowerPC chip as a RISC chip, but I think it's a misnomer in that case; RISC means Reduced Instruction Set Computer. The primary goal of RISC was to reduce transistor counts because a purely hardwired instruction decode (As was the case in the chips of the time) took up nearly all of the die area and transistors for the system.

So RISC was about putting more of the transistors to work more of the time. (By eliminating redundancies in the instruction decode). They did this in several ways; moving to a purely load/store architecture eliminated the complexity of many of the instructions. There's no need to have a register->register 'move' instruction at all; simply OR the contents of the register with zero, and store the result in the destination register. Assembly programmers find RISC even more tedious, because they have to jump through even more hoops (and using quite a few more instructions/lines of code) to 'get the job done.'

So if a RISC chip is about reducing the number of instructions (compared to a CISC chip), then the PowerPC hardly qualifies. It may have been intended to be one at the beginning, but as it is now, PowerPC has more instructions (without Altivec, which adds even more) than exist in a Pentium 4 or AthlonXP (Even if you include MMX/SSE/SSE2/3dNow!).

Re:32 compatibility mode vs. true 64 bit apps...

[Neon Spiral Injector]

I compiled everything from source for my Alpha, not one problem with 64-bit cleanliness. That was a problem in the early 90s. There are enough 64-bit chips around now, that every serious application has been compiled on one at some time.

GCC is already ready for the Hammer chips. If compiling for x86-64 you get code generated that can make use of mmx, mmxext, 3dnow, 3dnowext, sse, and sse2. It actually prefers those instructions over the old x87 functions by default.

I've heard that the Hammer is 2.5 times faster per clock than the lastest Athlons in 32-bit mode, and faster still in 64.

I WILL be building a machine around 2 of these chips as soon as the first Tyan board ships with PCI-X slots.

Re:32 compatibility mode vs. true 64 bit apps...

[nusuth]

The 64-bit address space is so obscenely big, it should be plenty even then... but, then again, so was 4 GB when the '386 came out...

When 386 came out we already had exhausted 20bit adress space we had and trying funny hacks with accessing the memory thorugh the keyboard controller chip (not really but A20 thing was close enough.) And 32 bits merely 4096ed it. The transition from 32 bits to 64 bits will increase the addressable space 4 billion times, which is a million times higher than four thousand of 386. That should make this transition quite a bit more durable.

Palladium?

[rmohr02]

The big question is whether or not Palladium will be built into this chip. Anyone know?

Years of optimizations are reaching their end

[godIsaDJ]

Since the advent of 32 bits processors there's been a huge amount of research trying to shrink the space taken by data-structures and similars. I've read of techniques devoted to save a couple of bits in Java classes for instance. Now we get addresses 64 bits long... I guess we can forget all of that... Any thoughts guys? Is it really worth trying to squeeze bits in object code if every 5/10 years processor technogy makes a leap?

Re:1TB

[TheRaven64]

Actually, it makes a lot of sense. Digital did the same thing with the Alpha. The architecture supports 64-bit addresses, but the current implementation does not. Who actually needs 64-bit addresses now? I suspect that anyone who does is not going to be using x86 hardware. Software can be written now which can take advantage of 64-bit addresses, and it will not need to be recompiled for newer versions of the series.

Re:8 way interleave

[10Ghz]

The benefits should be substantial. Besides the normal benefit of havin 8 CPU's you also get massive memory-bandwidth. Each prosessor has a memory-bank of it's own with 128bit mem-bus to it. But they can also use the mem-banks of the other CPU's (altrough there is a latency-penalty when doing that. But the latency is pretty good when compared to other architectures). So you could say that 1 Opteron has 1 x 128bit mem-bus, 2 Opterons have 2 x 128bit mem-bus, 4 have 4 x 128bit bus and 8 have 8 x 128bit mem-bus.

Re:Main Competitor = Itanium; Not Xeon

[Loki_1929]

Opteron is AMD's first real entry into the server market. AthlonMP was never truly meant for anything other than workstations or very low level entry servers. Itanium is Intel's offering for very strong, high performance servers. Their Xeon chip is the high-end workstation to mid-range server chip. All indications are that AMD will be targetting low to mid range servers with the Opteron.

Intel's point is that they don't believe anything other than high-end servers will use 64-bit chips effectively. AMD's point is that anyone can use whatever they like. A dual Opteron with 2MB L2 will most likely be targetted against dual Xeon machines. AMD will try to offer a better price point and the ability to run 64-bit applications to potential customers in their attempt to win partners. The launch of the Opteron had best go off MUCH better than the launch of the AthlonMP if AMD hopes to make it in the server business. Already weary of new products, big businesses will be looking for any excuse not to go with an Opteron. Even Intel has trouble convincing long-time customers to invest in new products, as evidenced by their dismal Itanium 1 launch. If the chipset and board problems we saw in the Tyan AthlonMPs creep up in any of the Opteron boards, AMD's cash cow will be seen in the business community as little more than the 'roo meat at McD's. That, potentially, could end up being the nail in AMD's coffin.

They have a lot riding on this launch, so let's all hope it goes off without a hitch. If it does, I think Xeon processors will be collecting dust within a year's time while Opterons slowly replace what's currently in the workplace. In very, very few circumstances will a company look at Opterons as an alternative for Itaniums. In terms of performance? Who knows; we haven't see benchmarks on production Opterons yet. If it's everything we're told it is, it may very well outperform the Itanium 2s vis-a-vis.

Re:Main Competitor = Itanium; Not Xeon

[fitten]

Nothing that I've seen on the 'net even hints that the Opterons will be that much of an increase in speed over the Athlon that exists today running at near the same clockspeed. The best figure that I've seen is only 20% improvement in speed in 64-bit mode because of the new registers.

The best database server comparison I've seen in a while is http://www.anandtech.com/IT/showdoc.html?i=1747 which shows that while the AthlonMP can keep up with the non-HT Xeons that are clocked near its PR rating, the Xeons are walking off from that point just by virtue of clockspeed, even before you add in HT.

Remeber, 64 != 32x2 in this case. Clock for clock, the Opterons are probably not going to be *that* much faster than an Athlon on many things. Personally, I'll be impressed if we see a 33% speed improvement at the same clock speed and I would bet that we could attribute a lot of that to FSB speed increases over the AthlonMP.

The Opteron's ace probably isn't going to be a huge performance increase. It's going to be that it can address a lot of memory.

Re:Main Competitor = Itanium; Not Xeon

[cbreaker]

Nothing hints to this? What about this very same slashdot article? They are giving the Athlon64's the "PR" ratings of Barton-core AthlonXP's at a much lower clock speed. This seems to be an indication of a pretty good speed increase in just running 32-bit software.

When running 64-bit software, it will depend on how heavily the software utilizes the extra data width. What type of application. And so forth.

It all depends on your perspective. Perhaps in your case, addressing 20GB of RAM is important to you. For me, 4GB is more then enough for any application I've used besides large database applications.

For me, a 20% speed increase out of the box before 64-bit software comes into play is quite acceptable. IMO, as long as the Athlon64 remains competitive with the Pentium 4 in terms of performance, then I'll love buying and using AMD chips now and in the future.

Besides, can you see of any other way the mass-market of computer users is going to be able to get their hands on 64-bit computers? I'm more excited about higher performance desktops then the high end server market.