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AMD Opteron Due In April
updog writes "Here's an article from Infoworld claiming that the new 64-bit AMD Opteron is ready to launch on April 22. Some of the notable features of the new chip are an address space capable of addressing up to 1 Terabyte of memory, the ability to link up to 8 processors without any external chips, and backwards compatibility with existing 32-bit applications ..." PapaFSmurf, meanwhile, links to a disclaimer-heavy article posted at amdboard.com which says that 64-bit Athlons may arrive in June rather than September as previously expected.
AMD's enchanted April
AMD's 64-bit alternative
By Tom Yager March 14, 2003
After years of hype, the AMD Opteron 64-bit processor will debut in April. The company and its shareholders might curse the rotten timing, but the current contracted market is actually the perfect setting for AMD's new technology. While other chipmakers scramble to adapt, AMD seems to have designed current business challenges and priorities into its architecture. Considering how long Opteron has been in engineering, AMD is either very smart or very lucky. Opteron may be an opportune solution for customers looking to consolidate their servers and reduce operating costs.
The advantages of AMD's new design are many. The most talked-about feature is the CPU's support for 64-bit applications. Unlike previous 64-bit processors, Opteron implements the full x86-32 instruction set. Software that runs on a Pentium III or AMD Athlon now will run unmodified on Opteron. Opteron-based servers will likely spend the majority of their time running the 32-bit Windows and Linux programs that businesses use today.
Software written to exploit Opteron's 64-bit capabilities will break through the barriers that prevent the x86 from running extremely demanding server and technical applications. A vastly expanded address space (up to 1TB of physical memory), a larger set of high-speed registers, and new instructions will take affordable servers to a higher level of performance. Running in 64-bit mode, an Opteron application can crunch through mountains of in-memory data and perform blazingly fast data transfers to network and storage devices.
Unlike other x86 processors, the Opteron CPU has the inherent ability to link up to eight processors without specialized chips. Every processor has three HyperTransport bus controllers for fast connections to other CPUs and devices. Instead of using an external memory controller, which complicates system design and adds latency, AMD links memory directly to each CPU. The design has plenty of headroom to accommodate faster memory and I/O devices. The only speed limit is the 19.2GB per second capacity of each chip's combined HyperTransport channels, which exceeds the top speed of the most capable PC server bus.
In systems that require more than eight processors, Opteron will rely on external chipsets to provide communications between CPUs. The fact that HyperTransport is already on the chip simplifies the engineering. Systems running two- and four-CPU configurations -- which account for most x86 server sales -- will ship in 2003. How soon larger systems appear depends entirely on market demand.
Answering critics
The chief criticisms leveled against the platform by Intel and critical analysts -- mainly that Opteron is immature technology and that Microsoft is dragging its feet porting Windows to it -- will prove groundless. The well-respected and thoroughly debugged Athlon x86 processor is the foundation of the Opteron chip. The remarkable HyperTransport bus that AMD uses to tie Opteron chips to each other and to I/O devices is already in widespread use. The DDR (double data rate) memory that AMD has chosen for its first implementation is inexpensive and readily available. AMD's chipset implements standard PCI-X and AGP ( Accelerated Graphics Port ) peripheral buses. System manufacturers and customers will have relatively few adjustments to make.
The Windows question is slightly trickier, but it isn't an issue Intel should press too hard. Yes, the sole 64-bit version of Windows runs on Itanium and Itanium 2. However, Microsoft has repeatedly stated that it strongly prefers AMD's 64-bit architecture to Intel's. Opteron is not stuck in the same spot as Intel at the launch of Itanium. Intel had to wait for Microsoft to announce its Itanium-specific port of Windows . Opteron already runs 32-bit Windows at full speed, while other 64-bit CPUs must use emulation to run most Windows software. Microsoft's engineering task, which it needn't hurry to accomplish, is to
AMD.com
The release date of April 22 was released a long time ago
(ie: January 21, 2003, just incase you didn't get the picture)
To make a pun demonstrates the highest understanding of a language
The Opteron is being launched on the 22nd of April. It was code named Sledgehammer, and is what Newisys and others are using. It is the server version of Hammer.
Athlon 64 is coming out in September. It is the desktop and mobile version of Hammer that was codenamed Clawhammer.
ignorance is bliss. googlefiberatx.com
here
and Athlon64 boards here
If you use a source-based distribution, like Gentoo, everything in your system will be compiled for your 64-bit architecture when it's installed. You'll be able to take advantage of your new 64-bit architecture right from the get-go.
Yes, much like the original 68k (68000, 68010) chips could only address 16 meg, but the instruction set was 32 bit and therefore able to go to 4Gig with subsequent chips without any problems (well, except the Microsoft-written AmigaBasic used the 8 upper bits as flags and therefore broke when the 68020 wanted to actually treat those bits as part of the address....horrible, horrible kludge).
Anyway, future opterons will be able to address a larger amount of memory without modifying the instruction set, and let's face it, by the time 1 TB of memory is affordable/useful, that original opteron is going to be long surpased.
Simple... The Opteron is designed for server use and has the massive cache etc while the athlon64 will be priced for home use.
Depends.
Linux has been running on 64-bit architectures for some time now, so 64-bit'ness isn't a new thing. And with distros like Debian that support everything from m68k up to Alpha a large portion of the issues have been taken care of already. Debian 'sarge' currently has 10058 packages, all of which compile and run (I'm not going to say all are 64-bit bug free, that would be stupid).
And also most Open Source apps are used on Solaris, Tru64, HP-UX, etc which are 64-bit. Windows may have a big transition ahead of it, but for the rest of us it'll be just like any other motherboard upgrade =)
However, Michael Dell has historically been Andy Grove's bitch...
I dount Dell will ever use an AMD chip, even if it means losing sales.
No, the ceiling is not stupid.
Limiting the physical memory to 40 bits reduces the cost of building other system components, such as chipsets and motherboards, dramatically. Further, 1TB of RAM is sufficient for the current market. That is 1000 1GB parts, to give it some perspective.
As customers begin to approach 1TB requirements, AMD only has to implement more lines. No need for any segmentation hacks. The ISA needs no modification. This is a pragmatic and wise design decision.
64 bits of address space is still very useful without having actual RAM to back it up. It means you can map large quantities of storage into RAM directly. For example; if you have 10TB of disk, you can map all of it into a single virtual address space and address it with simple offsets. Obviously this is useful for large databases.
Maw! Fire up the karma burner!
Windows is still going to use the swap file.
Why was this moderated as funny? It's certainly true for the NT series (including 2K and XP). Their VM strategy allocates all the ram (except the part reserved for the kernel) as disk cache, and all allocated memory is swap, cached by the main memory. This allows the kernel to dynamically tune the amount of disk cache used according to how much is required. It sounds insane, but is actually quite an elegant solution (in theory at least, I'm not convinced it works in practice. A lot of disk I/O throughput will kill system performance as all your apps get swapped out in favour of disk cache).
I am TheRaven on Soylent News
Cost.
These chips (for the first few years *at least*) will be low end or mid range small servers. Small in that they won't be competing with Sun Fire 15K servers which themselves only support physical memory of up to 576GB. No one will need those extra 24 memory address lines, so why build chips or motherboards with them?
Another way of looking at it is real-estate.
Currently 1GB dimms are the normal upper end, with a few 2GB dimms around.
At that rate, can you imagine the motherboard that could actually reach the 1TB RAM limit? 512 or 1024 dimm slots?....
Would that fit into the ATX form factor?
Manufacturing ICs is not an exact science. Very small impurities can render a die, or a part of a die unusable. The manufacturer can either throw these away, or disable the broken part and sell it as a crippled version. Intel's Celerons were just the P2/3s that had failed part of the cache tests. A lot of the difference between the Athlon64 and Opteron is cache size. A second is SMP support. The Opteron has 3 HyperTransport controllers on die that allow it to communicate with other CPUs with no 'glue' architecture. The Athlon64 will only have one, so any Opterons which have one defective HT controller can be sold as 2-way SMP parts, and those with 2 defective HT controllers will be Athlon64s (those with 23 defective HT controllers will be marketed as paperweights).
AMD has only developed a single CPU, and it will only manufacture a single CPU. It will market this as the most expensive Opteron. All the other versions are simply failed versions of this, with the broken parts disabled.
As an aside, you actually could enable the other half of the cache on some Celerons by mutilating the CPU a little. It was a particularly bad idea, since errors in cache tend to make your system rather unstable, but it could be done...
I am TheRaven on Soylent News
The linear (virtual) address is 64 bits, but only 48 bits are implemented. This means that pointers will only have the bottom 48 bits "arbitrarily" chosen. (The upper 16 bits are a sign-extension of bit 47). Future x86-64 revs can implement up to 64 bits if desired. Advantage: only 48 wires are needed to pass linear addresses around within the cpu.
The physical addresses are 52 bits, but only 40 bits are implemented. This means that the page tables can only assign pages to 40-bit physical addresses. Future x86-64 revs can implement up to 52 if desired. Why 52? The upper bits in the page tables that would be used for larger addresses are instead marked "available for software use". Advantage: only 40 wires are needed to pass around physical addresses, the caches only have to store 40-bit physical tags.
So in theory, one task could use 2^48 bytes of memory, but only 2^40 bytes would be in memory at any one time, the rest would be swapped out. The virtual-memory-manager (not the task iteself) would be responsible for keeping track of which pages are currently in memory.
I am not a sig.
Blockquoth the poster:
Your caution in this is reasonable, but don't forget that the GNU community is using GCC, which supports a gazillion of architectures, so:
So I would expect that the code GCC produces for x86-64 will be comparable to that produced for i386, and probably faster from the beginning, because of the extra registers. The extra size might affect some cache critical programs, but with the default integer size still being 32 bit, I wouldn't worry too much about that.
Vasilis Vasaitis
Late readers: please moderate at Newest First, with a low threshold, to promote late writers.
You will probably need a 32bit glibc. 32bit code runs in a different processor mode (think the V86 mode used in dosemu)
And you're getting this pricing for the Opteron from where? Everything I've been hearing has the low end stuff -=undercutting=- the current Xeon pricing, while still running more than standard Athlons/P4's.
Geez.
What makes the Opteron a server chip is the presense of three hypertransport links, the bus used for communication between multiple CPUs and other components such as the motherboard chipset. The Athlon64 will have only one. This is important since hypertransport, unlike say PCI, uses point-to-point links. The AGP and PCI bridges could be on separate hypertransport links and in theory we could see things like gigE controllers directly attached to the hypertransport bus.
Also, last I heard, the Opteron will use Dual DDR memory, while Athlon64 will have to make do with single-channel DDR. Recall that both Hammer chips (SledgeHammer, aka Opteron, and ClawHammer, aka Athlon64), have the memmory controller integrated onto the CPU.
For both of these reasons, the Opteron and Athlon64 sockets are incompatible (Socket 754 vs Socket 940). There's an old review with plenty of information here
One thing you are missing .
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Athlon was designed using technologies from
DEC Alpha 21064 and 2162 RISC processors.
Their "farther" Dirk Meyer came to AMD and
brought in an engineering team who succesfully
developed the Athlon
The lead design engineer for the Athlon
was the engineer that built the DEC Alpha EV6,
and thus a higher base architecture
was designed in and was already forward thought
for 32bit and a 64bit world
This was not well known by most ppl outside
of design circles, and hardcore hardware ppl
The former DEC designer has insight into
64 bit design when Athlon was released,
and the fact that the old irongate boards
were based on the DEC EV6 lend credence
A big suprise may be coming if they pull this
off, and I cannot wait to see it if it works
Benchmarks for 1st pass BIOS's are "always"
lower until they are tweaked and optimised
For that matter the OS's often have to be
tweaked to take full advantage of them
In time the Clawhammer, and Sledgehammer will
show their true abilities
Peace...
Ex-MislTech
google "32 trillion offshore needs IRS attention"
AMD's Opteron processor will be offered in three varieties:
Opteron 1xx series - Single processor workstations/servers
Opteron 2xx series - Dual processor workstations/server
Opteron 8xx series - Up to 8-way SMP servers
The first two are pretty directly targeting the market that the Xeons currently sell into, but the last one starts to touch on the Itanium's market. The Xeon tends not to scale well beyond 2 processors, and in fact, most Xeons won't work at all in anything more than 2-way systems (only the Xeon MP is certified for use in 4+ processor systems).
As for price, AMD hasn't announce any prices, but I think it's quite reasonable to assume that the 1xx series of Opterons will be quite reasonably priced (probably not significantly more than an AthlonXP or P4), the 2xx series will be priced similar to the Xeon (about 10-20% more than a P4 of the same clock rate), while the 8xx chips will cost about the same as a Xeon MP ($1000-$2000).
Of course, when it comes to servers, the processor is only one relatively small part of the equation, and so far all the Opteron servers I've seen have been pretty high-end systems, so I don't expect them to be cheap.