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Four Core Processor to Bring Tera Ops
panhandler writes "As reported at CNet and the Austin American Statesman, researchers at UT are working with IBM on a new CPU architecture called TRIPS (Tera-op Reliable Intelligently adaptive Processing System). According to IBM, 'at the heart of the TRIPS architecture is a new concept called 'block-oriented execution"' which will result in a processor capable of executing more than 1 trillion operations per second."
Exactly. The IA64/itanic/itanium instruction set provides for executing multiple instructions "simultaneously" (aka: pipelined with no interference) but the intel guy I heard from said it so far doesn't provide anything close to the improvements they hoped the feature might. Scaling it up to 64 instructions per clock is only going to help tasks which IBM supercomputers have already lost to beowolf clusters.
Wasn't the PS3 "Cell" chip made by IBM and Sony supposed to deliver 1 teraflop too?
That's throughput they're working on, which is great, but not the problem. Latency is the problem, not throughput. Try having large programs with lots of branches and/or syscalls: If the code is large enough, you'll spend more time bringing pages in from memory than actually executing your code, especially since you can forget about pipelining benefits...
Personally, I wish a company would throw out every idea from current memory, put a GB of cache on a chip, and get memory access times down to about 3 picoseconds. But memory doesn't have the marketing appeal that processors do, so we're screwed.
--That's the point of being root, you can do anything you want, even if it's stupid.