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Four Core Processor to Bring Tera Ops
panhandler writes "As reported at CNet and the Austin American Statesman, researchers at UT are working with IBM on a new CPU architecture called TRIPS (Tera-op Reliable Intelligently adaptive Processing System). According to IBM, 'at the heart of the TRIPS architecture is a new concept called 'block-oriented execution"' which will result in a processor capable of executing more than 1 trillion operations per second."
at Unreal Tournament ? Why, some have cool jobs.
Great... Just what we need, processors that can perform an instruction, then wait 40000 cycles for the next instruction to be read from memory. I wish we could see some memory improvements to go along with these.
Seriously, though, this will help break all the clustering records, provided we can come up with faster interconnects by then.
--That's the point of being root, you can do anything you want, even if it's stupid.
Will still take five minutes to boot into a login prompt. Some things never change.
A somewhat more informative link for more info. Would it really kill submitters to put a link to the actual project in their submission...
Nae bother
"This is yet another breach of our IP! Our fine researcher came up with this technology over 10 years ago, we have just ket it hidden for all this time. Unfortunately we wrote the patent-applications with invisible ninja-ink and they are being kept in a vault in our Fortress of Doom (tm), so we can't show them to anyone.
We expect IBM to pay us 5 billion dollars plus 4 x $699 for each CPU sold"
Lesbian Nazi Hookers Abducted by UFOs and Forced Into Weight Loss Programs - -all next week on Town Talk.
Does anyone remember the Pentium Pro? It was an extremely expensive processor. This was because of its strange system of connecting the CPU core with a massive amount of cache ram; production yields were very low, so fabrication costs were very high.
Imagine how high the failure rate would be with fabricating a CPU with four cores... I don't see how it would be practical unless it was with an extremely-high yield design such as the StrongARM.
The four cores add up to only 32 billion operations right now according to the CNet article. They project that they won't reach 1 trillion until 2010.
Hmmm... Pie...
But this reminds me of a growing trend, and that is that as soon as large infrastructures are finally completed (be it the transition to OS X or 802.11b) the technology becomes obsolete. However, the entire infrastructure must be replaced. I don't care how many gazillion flops this or any other processor can pull. They need to easily scale so that the entire infrastructure does not need replacing.
Quid festinatio swallonis est aetherfuga inonusti?
Africus aut Europaeus?
Exactly. The IA64/itanic/itanium instruction set provides for executing multiple instructions "simultaneously" (aka: pipelined with no interference) but the intel guy I heard from said it so far doesn't provide anything close to the improvements they hoped the feature might. Scaling it up to 64 instructions per clock is only going to help tasks which IBM supercomputers have already lost to beowolf clusters.
If anyone in any way shape or form mentions the word beowulf, expect a swift kick in the nuts by your's truly.
That is all
Hacker Media
using namespace slashdot;
troll::post();
Wasn't the PS3 "Cell" chip made by IBM and Sony supposed to deliver 1 teraflop too?
....that I've had Doug Burger and Steve Keckler as professors here at UT, and not only do they know their stuff, but they're great professors as well, and they really seem to intimately care about the technology. They have a great sense of humor too (such as Dr. Burger complaining that he doesn't even have root access to his own machines :-P)