Sun Unveils Direct chip-to-chip Interconnect

mfago writes "On Tuesday September 23, Sun researchers R. Drost, R. Hopkins and I. Sutherland will present the paper "Proximity Communication" at the CICC conference in San Jose. According to an article published in the NYTimes, this breakthrough may eventually allow chips arranged in a checkerboard pattern to communicate directly with each other at over a Terabit per second using arrays of capacitively coupled transmitters and recievers located on the chip edges. Perhaps the beginning of a solution to the lag between memory and interconnect speed versus cpu frequency?"

Comments

Timing?

[afidel]

I wonder if this release might have been pressed forward a bit to squelch some of the talk about Sun losing their will to innovate after Bill Joy left.

Replacing Network-on-Chip/System-on-Chip

[KarmaPolice]

This could prove very interesting as the speed usually drops when "leaving the chip" to do communications. There has been alot of research to develop protocols to ease on-chip communication when several ICs are combined on a single chip. If Suns technology can stand the test, NoC/SoC products could reduce it's time-to-marked dramatically...smaller and faster devices for everyone!

BTW: I didn't RTFA since it requires (free) reg.

Fast today Slow Tomorrow

[Anonymous Coward]

That is the nature of the beast.

Remember how excited you were to get your hands
on a 386 machine?

The thrill of your first encounter with a 286 screamer?

Upgrading to 16k from 4k on your TRS-80?

Your first disk drive for your Apple 2?

It's all relative.

So enjoy

Perhaps a physical base for Neural Network?

[BlankStare]

I wonder if this hardware computing model could provide the first real base for Neural Network computing? As far as I know, any neural network is currently emulated on linear processing machines.

FINALLY!

[JoeLinux]

Someone gets it. As an Electrical Engineer-in-training, I was always frustrated with people who got these big bad processors and wondered why their improvement was minimal.

They never quite grasped that the biggest bottleneck is between the processor and memory.

My EE instructor always said that they could improve performance by doing one simple thing: make the interconnects on the motherboard between the motherboard and RAM rounded instead of cornered. You could then increase bus speed as you wouldn't have magnetic loss at the corners like you do now.

You fix that, and you can see a SUBSTANTIAL improvement in performance. The only thing that can be done beyond that is to get a Platypus drive (Solid state "Hard Drive" made from Quikdata made from DDR RAM). Then you reduce your access time to your hard drive from milliseconds to nano/microseconds.

Re:FINALLY!

[hackstraw]

Other people "get it". If you go to UVA, you might want to talk with Dr. McCalpin, and take a look at the stream memory benchmark.

Memory bandwidth is a bottleneck, not the biggest. It depends on the application. Sometimes an app is CPU bound, disk bound, network bound, or memory bound (or graphics card bound if 130FPS is too slow for your eyes). Also, chip-to-chip interconnects will not change the memory bandidth issue, because if the data does not fit on the chips or thier cache, then its going in memory.

Also, this is for scaling. Think beowulf. For those machines, the data must go from the cpu -> memory -> network interface -> switch -> network interface -> memory -> cpu. Yes, bandiwidth is an issue, but there is also latency, which would be very low with these kinds of chips.

A side note, I work with a guy that soldered chips together like this which had native parallel processing instructions about 20 years ago.

Re:IANAEE (I am not an electrical engineer)

[Usagi_yo]

Alot of reasons. We'll start with large complex chips. No, the pins aren't at the end of the chip, they are underneath the chip. BGA, CGA, LGA, ball grid, colume grid or land grid array.

Then we'll go to ... well, they sorta did. They just enclosed it into one big chip.

Then of course Heat and cooling and power requirments.

Then onto manufacturability and repairability. Don't want to have a $15k board that has to be thrown away whenever there are problems with it. You do want to be able to repair it.

Next on to glue logic or glue componants such as current limiting resisters, pull ups, pull downs, bypass and decoupling capacitance.

Sun may be ahead in other areas, too

[Mr. Ophidian Jones]

Normally I don't pimp Sun, but here's something that makes me think they still have a finger on the pulse of things:
Read about plans for Sun's "Niagra" core

I understand they hope to create blade systems using high densities of these multiscalar cores for incredible throughput.

There's your parallel/grid computing. ;-)

Increase yield?

[mmol_6453]

...in particular chips that may require different manufacturing processes.

Or at least portions of more complex circuits where part of the circuit may not warrant the added cost of SOI, 90nm, or strained silicon.

But then, those divisions are already made. AMD, for one, is working on recombining those parts. As an example, consider AMD's putting the memory controller on the CPU die.

I am curious, however, as to whether you could have more than one silicon die in the same ceramic casing. This would let you combine different parts made using different techniques. The CPU and L1/L2 caches could be on a high-cost process, with the L3 cache and memory controller being built with cheaper processes.

Placing more emphasis on cost savings than on performance, you could build the L1 instruction cache with a slower process than the L1 data cache. Or you could leave all of L1 on the same process and split L2 into instruction and data caches, with different processes.

If you wanted to ramp up CPU speed without a major hit to your performance, you could reduce the feature size of the core and L1 caches, and put L2 on a slower, more reliable process. That way, you could ramp up core speeds without having as much worry about yield loss from cache failure.

Helluva way to increase yield, and it gives the designer a LOT of options.