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Intel: Metal in Future Chips = Less Leakage (updated)
securitas writes "Intel is contemplating using metal instead of silicon in future chips for the 'transistor gate, which controls whether a transistor is on or off' and the 'dielectric, an insulating layer below the gate,' which are respectively made of silicon atoms and silicon dioxide. 'Millions of minuscule switches that make up silicon chips leak electricity when they're supposed to be shut off. To compensate, engineers have increased the current, driving up power consumption, decreasing battery life for portable devices and generating more heat.' AMD has also experimented with metal instead of silicon. By moving to metal AMD and Intel expect to reduce electricity leakage. More from AP via SeattlePI and the Miami Herald." Update: 11/05 15:25 GMT by T : Read on below for some information from Intel on why this is a good thing.
gManZboy writes "Following up on the Intel news that about using metal in chips -- here's an explanation from Shekhar Borkar (Intel Research Fellow) about why heat, power, and sub-threshold leakage, not transistor size, are the real challenges to Moore's law. Apparently, in order to make chips much faster, we're going to have to pump more electricity in then anything else in our houses -- and they'll soon be as hot as a nuclear reactor -- no, really."
In the AMD article the use of Nickel is mentioned.
You are thinking of the Copper traces instead of Aluminium, the transistors remained Silicon. Here they are talking about metal transistors.
The history of Moore's Law.
Or if you are interested in Moore's original paper, you can find it here.
I want to drag this out as long as possible. Bring me my protractor.
The chemistry of the non-silica gate dielectric requires that the gate itself be non-silicon, and metals are better conductors anyway. (For larger transistors, we're already running into trouble from the distributed resistance of the gates.)
Hope that helps.
Lacking <sarcasm> tags,
Why is VLIW not more popular? Because compiler technology isn't yet good enough and current VLIW designs have restrictions that get in the way of the best performance.
Over the years, there have been many attempts to use techniques such as VLIW, which sound great on paper, but don't do well in practice. What have worked the best, at least through the 90s, are architectures that do a lot of simple things fast.
You can make VLIW fast, Intel has managed that, but at great cost in both silicon and software.
Be careful when making generalizations about a processor line such as the P4 - there have been quite a few P4 generations, each better than the last. Latencies have gone down.
I think that parallelism (eg. HyperThreading, multicore, etc.) is where the real-world performance gains will come from. Single-threaded benchmarks don't accurately reflect realistic workloads.
Here is an article explaining low-k dielectric. I believe this is a shipping product on the Power4/4+ based systems and it is in the EXA chipset on the x365/x440/x445/x450 Intel servers, and the Apple G3 and G5. The xSeries products even have little copper BB's in the grill of the system to symbolize that they use copper based technology.
As a rock-in-roll Physicist once said, No matter where you go, there you are.
Just checking, because it souded like these people were hoping to do just what you mentioned as being heavily fought. And so far, they haven't been killed as far as I know.
I, for one, welcome the death of our diamond-scarcity-based overlords.
Actually, it's currently being done by Apollo Diamonds and Gemesis, which was mentioned above. De Beers is fighting them as hard as they can, but even if they convince the public that manmade diamonds aren't worth anything as jewelry, they will still be able to use them for computing. However, production is not quite ready for large-scale chip manufacturing, which is why Intel and others have not yet turned to diamonds.
No. The bonds between silicon atoms are covalent. A metal (e.g. copper) has a "cloud" of electrons free to move around in the lattice. Silicon is a semiconductor, with the charges bound to the atoms except when there's enough energy (typically thermal) to kick them loose.
Lacking <sarcasm> tags,
The dielectric layer mentioned in some studies is Hafnium dioxide (HfO2). This is an insulator, not a conductor. HfO2, is good because it is a high-k material and it is thermodynamically stable in contact with Si.
One reason for replacing polysilicon with a metal is that the HfO2 layer is not compatible with the polysilicon deposition process. Defects form in the HfO2 layer during the polysilicon deposition step. Another reason for replacing poly with a metal is to avoid poly depletion effects. Essentially, poly still behaves as a semiconductor, so a charge depletion layer forms near the poly/dielectric interface. This depletion layer acts as an insulator and has the same effect as increasing the thickness of the dielectric layer (which is what we're trying to reduce). The increased thickness reduces the capacitance, which needs to be large for the transistor to function properly. Unlike semiconductors, metals do not form a depletion layer.
I'm about 6 months away from my PhD in semiconductor physics.
They mean metal oxides. Leading candidates are Halfnia and Zirconia. These are "High-K dielectrics".
Using both reduces the Effective Oxide Thickness (EOT) of the gate dielectric. For the same thickness material, high-k dielectrics look like a thinner amount of silicon dioxide. Metal gates eliminate depletion effects in the gate (poly-depletion), which also makes the oxide look thinner.
With lower EOT, the gate has better control of the channel, so leakage goes down.
the materials for a capacitor's contacts have nothing to due with it's ability to store charge (thus its capacitance). it is only a function of the device's dimensions and its dielectric.
Silicon gates can be self-aligning. Once you've got gate oxide, deposit a layer of polysilicon and pattern it, then use the remaining poly as a mask for the gates while the rest of the oxide is removed.
I do know I'm forgetting another difficulty in working with GaAs, anyone care to remind me why GaAs is not as common as silicon today?
There are several. The defect densities in compound semiconductors are much higher than silicon, limiting size. The materials aren't as mechanically stable as silicon, which also limits size due to misalignment. Also, complementary FET structures are hard to get right (which is why most compound semiconductor circuits today are basically bipolar.)
I suspect that I'm also forgetting a few. It's been a while for me, too.
Lacking <sarcasm> tags,
Tantalum oxide is a good high-k dielectric, but it is not thermodynamically stable in contact with Si. As a result, Ta2O5 reacts with Si during the high temperature (>900 C) anneals necessary to activate the Si dopants. These unfavorable reactions ruin the devices and as a result Ta2O5 has largely been abandoned as a potential dielectric in Si transistors. Ta2O5 is used for capacitors in DRAM memory devices.
Electrical grade silicon (EGS) has a long purification process that it must go through to be of sufficient quality to make chips from. To give an example, there are roughly Avogadro's number of silicon atoms in one cubic centimeter of silicon (5.5x10^22 atoms / cc). After being purified, the MAXIMUM impurity concentration is ~10^14 atoms / cc. This is around 1 part per 100 million. The best laboratory grade Si is 100 times better than that!
Contrast this with diamond: even the best artificial diamonds have so many impurities that you can see them with the naked eye. So even if diamond semiconductor chips can be made (SiC is much more likely) we won't be able to use them for anything like what we do now until the purification process is improved.
As for the phonon question: in crystals the quantum of atomic motion is called a phonon. Electrons can scatter off of phonons, reducing the mobility and hence increasing the resistance. Two ways around this: lower the temperature, which suppresses the creation of phonons, or use a heavier material, which is harder to move and hence phonons take more energy to create. Using a metal gate dielectric (heavier material) traps any phonon which touches it, reducing the concentration of phonons near the surface, where the conduction electrons are.
You are thinking of the Copper traces instead of Aluminium, the transistors remained Silicon. Here they are talking about metal transistors.
Not true at all. The copper in IBM's process is for interconnects, not traces. I'm not sure what metal they use for the traces, but it's probably aluminum and definitely not copper. The connection between layers (interconnect) are copper plugs.
The metal intel is talking about is strictly for the gate terminal connection of the transistor. The transistor is still doped silicon or gallium arsenide or whatever semiconductor they are using.
Intel is actually talking about replacing the gate dielectric (which is silicon dioxide currently, even at IBM) with a metal or metal oxide, which has a higher dielectric constant. Higher dielectric constants mean a more effective gate for the same thickness, or the same gate effect for a thicker layer (and hence less leakage).
Intel is also apparently talking about replacing the polysilicon gate with an actual metal gate. Polysilicon is used for gates because it doesn't melt when the chip is annealed (an important processing step), like metal would. Intel's innovation is apparently figuring out a way to get around this problem.
Nope, the traces are copper instead of aluminium here is an IBM article from 2000. Unless "wiring" and "traces" no longer mean the same thing.
I dont see any mention of the type of metal that would be most suitable. I'm sure all metals are n't created equal.
Actually, two types of metal are probably needed. One for nmos transistors and another for pmos transistors. Nmos and pmos transistors have different threshold voltages (the voltage at which the device turns on), but ideally you would like both types of transistors to switch at the same voltage. The threshold voltage of a device can be shifted by modifying the "workfunction" of the gate metal. The workfunction is the energy required to remove an electron from the metal surface.
One reason polysilicon gates are used in conventional CMOS is that the workfunction of polysilicon can be modified by changing the level of doping and the type of dopant material (usually B, P or As). Thus, polysilicon gates can be used for both nmos and pmos transistors and by varying the doping, both types of devices can have the same threshold voltage.
Shifting the workfunctions of metals, using dopants is not so straightforward. As a result it will probably be necessary to use two different metals having different workfunctions for nmos and pmos transistors. Further complicating matters is the fact that the gate metal can interact with the dielectric material, modifying the effective workfunction and thus the threshold voltage. So, while the isolated metal may have the necessary workfunction, the workfunction may shift when the metal is part of a device. Thus, a lot of testing and experimentation is needed to find a metal that has the proper workfunction after it has been put into a device.
Yes, the type of metal is important due to the workfunction of the metal. This determines the potential interactions between the semiconductor and the metal, which affects things like device threshold voltage.
Vote for Pedro
The code name Coppermine had NO relationship with the metal used inside the chip. It was still an Al-on-Si chip, just like Katmai. Tualatin (last P-III core) and Northwood (second P4 core) were the first x86 Cu-on-Si chips from Intel (targeting Mobile/Server and Mainstream markets, respectively).
Additionally, AMD was making Cu-on-Si chips back at the Thunderbird (first "L2 cache on core" Athlon) debut. All cores that came from Fab 30 in Dresden were Cu-on-Si while all cores from Fab 25 in Autin were Al-on-Si. Palomino (first Athlon XP core) was made entirely at Fab 30 and thus all Palomino cores were Cu-on-Si.
IBM has been producing Cu-on-Si cores since 1998 (PowerPC 740, IIRC) and producing Cu-on-SOI cores since 1999 (PowerPC 750). Where do you think AMD got their SOI technology?