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Intel To Produce 65-Nanometer Chips In 2005
Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."
The relative importance of leakage increases at smaller geometries, but for all geometries on the near horizon, the increase isn't enough to outweigh the decrease in 'normal' (switching) power usage. This will probably change around 40 nm, but at 65 nm we're still making serious improvements.
I've had this sig for three days.
On an individual-gate basis, smaller gates use less power, since there's less capacitance at the gate to charge or discharge. Of course, smaller gates mean more components in a given area, which increases power consumption.
These two effects should just about cancel out, since gate capacitance increases with the square of the feature size, and the number of gates drops at the same rate.
Which leaves you with the other effects (including leakage), which are all worse with smaller gates. So, a maximum-size part will have a higher power consumption on a smaller process, but if you took an existing design (like a Pentium 4) and rebuilt it on a smaller process, you should get a lower power consumption (and smaller/cheaper die size).
-Mark
Nah, it's actually the opposite of that.
Since electrons have less distance to travel, the resistance of the dielectric is less and less will leak. In extreme cases, for very small geometries, quantum tunnelling becomes an issue as electrons disappear on one side of the gate and appear on the other.
But as other posters said, leakage is currently still fairly insignificant compared to the huge WOOOSH of power that goes into the chip when things switch. Although leakage is becoming now more important for devices that sleep and stop their oscillator to reduce power-- passive power consumption, for the same process, is directly proportional to feature size, die size, and the square of the operating voltage.
Also, for complete systems, SOI has a problem in that memory density tends to be much lower... so your caches have to be smaller if they are on-chip.
-- Erich
Slashdot reader since 1997
This 2001 paper suggests that about three silicon atoms fit into an nanometre and that they could space "bumps" at 38 nanometres. But that was a long time ago.
Hmm... I'm having trouble visualising 0.57 microns square. Lets see - even with these reduced cell sizes, you'd need 3600 square meters (half the size of a football pitch) of SRAM to have one bit per person on the world.
Yes, I know its the fault of the metric system, everything would have been easier with mils, Angstrom and squarefeet.
But the correct result is 0.0036 m^2. Does a Gigabyte of Dram (=8 Billion Bits), which is obtainable in todays technology, take up a football pitch? no!
1 square meter is NOT 10^6 square microns.
But bonus points for being the first one to make this mistake in this thread, someone always does.
It's not wasting time, I'm educating myself.
BTW, this is apparently being done at the fab known as D1D in Hillsboro - this isn't a small scale research lab, it's a full size production fab. That it is being done there indicates it isn't as far away as you might think.
As for your comment about SOI, why does it need to be so black and white? It's always a judgement about the benefit versus cost, and it's always possible to get the same result more than one way. IBM made a strategic decision to go down the SOI path some time ago. Intel has gone down the strained silicon path. Each has its advantages and costs, and either camp could switch to the other if they saw an advantage in doing so. But given that they have made different choices, it's unlikely that one is "wrong" and the other is "right"
At this point, without some sort of additional chip technology(SOI, tri-gates, etc), it seems very likely that power consumption will definately stay even, if not go up entirely. Every new scale of technology is a bigger problem to make work, as the (known) laws of physics aren't moving with it, posing a very absolute barrier. Whereas 350nm, 250nm, and even 180nm went off without a hitch(with companies even manging to stick some Cu in there), 130nm was a big problem for AMD and TSMC(makers of Nvidia's GPU's prior to the IBM), and even Intel was having problems depending on who you ask.
Currently, 90nm is looking especially difficult, as Intel has had to push P4's based on the technology back twice from when they originally intended to release them, putting us currently at Q1 2004. That introduction isn't looking very pretty either, with the Prescott being dubbed the "100wt monster"; a new cooler design is nessisary in most cases for Prescott CPU's, along with the new BTX case standard(repositions the CPU for better cooling) for later on in the 90nm cycle, and all of this is for a chip that runs hotter than its 130nm counterpart(Prescott only adds another 512KB of L2 cache and SSE3, along with general core fixes; this shouldn't have resulted in a net gain against the overall power use unless the shrink didn't drop consumption significantly).
Either way, Intel is going to be able to pull off 65nm, but without the aid of other technologies, all they're going to end up with is a very hot chip that will have little chance at a major clockspeed ramp-up in its lifetime.
The pitch between atoms in a plane in a silicon crystal is about 0.14nm.
There are a number of things going on here, but a few important things to think of.
First off, with previous shrinking of the manufacturing process you could run the processor at a lower voltage. Most 500nm chips ran at 3.3V, 350nm chips ran at 2.8V, 250nm chips ran at 2.0V, 180nm chips ran at 1.75V and 130nm chips now run mostly at 1.55V. As you can see pretty quickly though, the difference in voltage isn't as much as it used to be, and with 90nm production, that difference is pretty much zero, most 90nm chips will probably run at about the same 1.55V of current (130nm) chips.
Second, the Prescott does add a bit more than just cache. Alongside the new SSE3 instructions, Intel is also making some fairly major changes to the P4 core, fixing some of the potential problem areas. I haven't heard 100% official confirmation, but apparently it adds a barrel shifter (should be very noticeable for D.net clients if they do) and fixes some of the scheduling issues with multiplications. These changes are going to result in extra transistors, and extra transistors means more power.
Also, the Prescott is supposed to improve hyperthreading. This is a good thing from a performance standpoint, it means that you'll get more of a performance boost from running two threads at once. The downside is that it means that the processor pipeline will be packed more fully, again increasing power consumption.
In short, there's lots to consider, no easy equation to get you the power consumption of the new chip.