Intel To Produce 65-Nanometer Chips In 2005

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Comments

Reduce Power?

[brandido]

According to the article,

Reducing the size of the chip improves performance, reduces costs and can potentially cut energy consumption. In a nutshell, electrons have a shorter commute in 65-nanometer chips, so performance goes up. The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.

However, it was my understanding that power consumption will often go up with smaller geometries as leakage current increases with the smaller gaters. Can anyone elaborate on this?

Re:Reduce Power?

[John Courtland]

There's all sorts of problems when you get that small and fast. EMF interference, gate jumping, electron migration. The thing basically is a small radio transmitter, and starts causing itself problems just by running so fast. They need to really start designing more intelligently, unlike (as a previous poster stated) "ramping it up".

Re:Reduce Power?

[batura]

While leakage is a big problem, its not as big as the power usage per switching transisitor, which if P = C * F * Vdd^2. This is the power consumption when the transistor goes from its high to low state and reducing the distance between gates reduces the capacitance in the wire. At really high frequency, you can make any wire seem like a capacitor, so its important to reduce the lenght of wire you're using.

Sure, you can cram more circuits on a chip...

[Not_Wiggins]

But, you'll also be incuring greated magnetic field interference. Heck, the thing will also generate more heat as driving current through smaller traces creates more "friction;" the chip might break itself simply under thermal load.

Just because you can make it smaller, doesn't mean it'll function properly. There's a theoretical limit to how small traces can go before the interference makes signaling impossible.

I can't wait to see how many processors get "down-binned" once they ramp up production with this tech. 8/

Useless metrics

[tttonyyy]

Hmm... I'm having trouble visualising 0.57 microns square. Lets see - even with these reduced cell sizes, you'd need 3600 square meters (half the size of a football pitch) of SRAM to have one bit per person on the world.

Assuming a constant 50W/sqr.mm, that'd be 180GW of heat. Someone find me a heatsink for that baby!

Re:thats all fine & dandy

[NWRefund]

Just because they say, "You can get a 40 to 50 percent increase in clock speed with no further improvements," doesn't mean they aren't going to implement further improvements anyway.

Does it say in that article that the new processor will be 32 bit x-86? No. It doesn't give any specifics at all, as a matter of fact.

Intel has a very talented marketing department. Whether or not you like them as a company, you at LEAST have to admit that. This is exactly as someone else has mentioned - it is a slap in the face to AMD who, try though they might, are still drowning in red ink.

Don't berate this new manufacturing process until you have a little more info on what they're going to make with it, hm?

65nm when 90nm isn't even out yet? hm

[David Jao]

Look, I am not a chip fabrication expert. I am merely a sideline observer. But based on my observations, Intel will probably not make it to 65nm in 2005.

My position is based on nothing more than simple counting:

• Intel achieved 250nm process technology (deschutes) in January 1998
• ... 180nm (coppermine) in October 1999, although availability was scarce until January.
• ... 130nm (northwood) in January 2002
• ... 90nm (prescott) is not out yet, although it is supposed to be out in fourth quarter 2003. I'm going to go out on a limb here and predict January 2004.

Their track record is clear: the average time between circuit size improvements is two years. Based on their history, 2005 would be a stretch, with the most likely release date falling somewhere in early 2006.

2005? Maybe the end of 05

[doormat]

Look at all the problems they are having with the 90nm process right now? That thing is leaking current like you wouldnt believe. Power dissapation is 90-100W. Heat is a big issue. I'm thinking something is going to have to happen to lower current bigtime. Remember thats 100W at 1.3V or so, for 77A, whereas the current P4's use 70W or so at 1.5V, for 47A.

Re:Is that enough?

[Hoser McMoose]

Originally Moore's law stated that transistor density would double every 12 months. That was fairly quickly changed to say that it would double every 18 months. The current "law" states that transistor density doubles about every 24 months.

Long story short, we haven't really been following Moore's law for a little while, though we do continue to double the amount of bits we can stuff onto a piece of silicon at a fairly rapid pace. Intel's plan to bring out 65nm chips before the end of 2005 continues this trend.

FWIW IBM is also looking to bring out 65nm chips by late 2005/early 2006, while AMD is hoping to get their 65nm fab process up and running in their new fab early in 2006. TSMC and UMC are likely to follow in mid-2006, though I haven't heard any official comments from either.

Intel makes miracles happen

[jackstack]

I dunno how many people really appreciate how incredible the contributions that Intel has made.

I recently learned that thier 3GHz processors possess 1.2nm (12Angstroms) gate oxide thickness. I'm not exactly calibrated, but it can't be more than a Si atom conected to an Oxygen connected to a Si atom conected to an Oxygen along the thickness direction. And this is *consistently* done across a 300mm wafer (~1 foot!). It's just insane!