Intel To Produce 65-Nanometer Chips In 2005

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Comments

Re:Reduce Power?

[addaon]

The relative importance of leakage increases at smaller geometries, but for all geometries on the near horizon, the increase isn't enough to outweigh the decrease in 'normal' (switching) power usage. This will probably change around 40 nm, but at 65 nm we're still making serious improvements.

I believe it works like this:

[mbessey]

On an individual-gate basis, smaller gates use less power, since there's less capacitance at the gate to charge or discharge. Of course, smaller gates mean more components in a given area, which increases power consumption.

These two effects should just about cancel out, since gate capacitance increases with the square of the feature size, and the number of gates drops at the same rate.

Which leaves you with the other effects (including leakage), which are all worse with smaller gates. So, a maximum-size part will have a higher power consumption on a smaller process, but if you took an existing design (like a Pentium 4) and rebuilt it on a smaller process, you should get a lower power consumption (and smaller/cheaper die size).

-Mark

Re:I have no doubt they can do it.....

[Erich]

SOI has a much different design methodology. If you are Intel and have a really great design flow for non-SOI, it may not be as simple as "just go to SOI."

Also, for complete systems, SOI has a problem in that memory density tends to be much lower... so your caches have to be smaller if they are on-chip.

Re:Questions.

[henrygb]

This 2001 paper suggests that about three silicon atoms fit into an nanometre and that they could space "bumps" at 38 nanometres. But that was a long time ago.

Ooops, for got to square properly

[FuzzyDaddy]

1 square meter = 1 meter*1 meter = (10^6 micron * 10^6 micron) = 10^12 square microns.

1 square meter is NOT 10^6 square microns.

But bonus points for being the first one to make this mistake in this thread, someone always does.