Intel To Produce 65-Nanometer Chips In 2005

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Comments

Intel culture

[BiggerIsBetter]

What a beautifully telling Intel quote that is, "You can get a 40 to 50 percent increase in clock speed with no further improvements". Just keep ramping it up boys.

Reduce Power?

[brandido]

According to the article,

Reducing the size of the chip improves performance, reduces costs and can potentially cut energy consumption. In a nutshell, electrons have a shorter commute in 65-nanometer chips, so performance goes up. The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.

However, it was my understanding that power consumption will often go up with smaller geometries as leakage current increases with the smaller gaters. Can anyone elaborate on this?

Re:Reduce Power?

[John Courtland]

There's all sorts of problems when you get that small and fast. EMF interference, gate jumping, electron migration. The thing basically is a small radio transmitter, and starts causing itself problems just by running so fast. They need to really start designing more intelligently, unlike (as a previous poster stated) "ramping it up".

Re:Reduce Power?

[addaon]

The relative importance of leakage increases at smaller geometries, but for all geometries on the near horizon, the increase isn't enough to outweigh the decrease in 'normal' (switching) power usage. This will probably change around 40 nm, but at 65 nm we're still making serious improvements.

Re:Reduce Power?

[batura]

While leakage is a big problem, its not as big as the power usage per switching transisitor, which if P = C * F * Vdd^2. This is the power consumption when the transistor goes from its high to low state and reducing the distance between gates reduces the capacitance in the wire. At really high frequency, you can make any wire seem like a capacitor, so its important to reduce the lenght of wire you're using.

Moore's Law

[worst_name_ever]

In keeping with Moore's Law

Well, more like "keeping Moore's Law a self-fulfilling prediction for yet another generation of processors". ;)

This is great news

[Timesprout]

The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.

For all those lazy or out of condition electrons out there, they only have to travel 35 nanometers now to get some work done.

I have no doubt they can do it.....

[Selecter]

But it seems to me to be rather premature announcement, supposing these chips will be out when Intel says they will be. I think Intel is starting to feel the heat from quarters they didnt expect, like AMD and Apple via the good graces of IBM. Athlon 64 looks like a winner and so does the IBM made G5. IBM and AMD both have great looking roadmaps for the future.

This smells like a another smear piece by Intel to me, kinda like paper launching the P4 Emergency Edition on AMD's rollout day for the Athlon 64.

Boo. Hiss.

Re:I have no doubt they can do it.....

[Selecter]

I thinks it's premature to build a few test SDRAM cells and then magically announce they are going to build chips using that tech in possibly less than 1 year and 1 month. It's far more likely they will not meet that target, given the real hurdles of fully implementing that process to overcome. A few SDRAM cells does not a P5(6?) make.

Also, someone is not telling the truth.

"The 65-nanometer chips will not include the IBM-touted silicon-on-insulator technology, either. "We have not seen any significant performance advantages with SOI," Bohr said."

Well, who is it? IBM and AMD are going with it. Who's wrong, Intel or IBM/AMD? I'd like to know.

Re:I have no doubt they can do it.....

[Erich]

SOI has a much different design methodology. If you are Intel and have a really great design flow for non-SOI, it may not be as simple as "just go to SOI."

Also, for complete systems, SOI has a problem in that memory density tends to be much lower... so your caches have to be smaller if they are on-chip.

40 to 50 percent increase?

[Anonymous Coward]

"You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Yeah, I get those "40 to 50 percent increase" emails all the time...I've been deleting them as fast as they come in.

Ohhhhhh...wait.... He said CLOCK, not COCK
nevermind :-)
TDz.

Sure, you can cram more circuits on a chip...

[Not_Wiggins]

But, you'll also be incuring greated magnetic field interference. Heck, the thing will also generate more heat as driving current through smaller traces creates more "friction;" the chip might break itself simply under thermal load.

Just because you can make it smaller, doesn't mean it'll function properly. There's a theoretical limit to how small traces can go before the interference makes signaling impossible.

I can't wait to see how many processors get "down-binned" once they ramp up production with this tech. 8/

. . should have been 64 nanometers

[Anonymous Coward]

If they were really thinking ahead, they should have tried for 64 nanometers. Then, when the chip size halves every few years according to Moore's law, it can stay a whole number of nanometers for a few more years yet.

Moore's "Law"?

[nacturation]

I've always wondered why it's called Moore's Law. After all, it's not something which is mathematically provable. You'd figure computer scientists and systems engineers would be a bit more rigorous and call it Moore's Theorem, Moore's Axiom, or Moore's Postulate (I'm not sure what the best terminology is for this kind of conjecture). Granted, it has been approximately held, but there's no underlying reason why processor speed couldn't increase by an order of magnitude in a few months given the right implementation.

Re:Moore's "Law"?

[taradfong]

Similarly, "Murphy's Law" was supposed to be called "Murphy's Axiom" but something got screwed up.

Is that enough?

[nnnneedles]

50%, hmm.

doesn't Moore's law require 100% increase every 18 months? Yeah I know Moore's law isn't really about speed, but still.

I believe it works like this:

[mbessey]

On an individual-gate basis, smaller gates use less power, since there's less capacitance at the gate to charge or discharge. Of course, smaller gates mean more components in a given area, which increases power consumption.

These two effects should just about cancel out, since gate capacitance increases with the square of the feature size, and the number of gates drops at the same rate.

Which leaves you with the other effects (including leakage), which are all worse with smaller gates. So, a maximum-size part will have a higher power consumption on a smaller process, but if you took an existing design (like a Pentium 4) and rebuilt it on a smaller process, you should get a lower power consumption (and smaller/cheaper die size).

-Mark

Cool, but...

[EverDense]

Wouldn't Moore's Law have failed by now without AMD competing for market share?

Re:Cool, but...

[moehoward]

No. Intel is always competing with itself. They want to make their products obsolete as soon as possible so that people upgrade.

Please mod parent back down, as I have made him look foolish.

Re:PC Toaster

[jon787]

what is scarier, you thought of it, or somebody did it

Not really.

[TCaM]

From all I have read the new AMD fab, like most any other will start out at a given process size, likely 90nm in this case, but will be ramped down so to speak. Do you really think they are buying near a billion dollars worth of equipment that isn't in any way upgradeable? Do you think Intel builds entirely new fabs for each new process and just takes the wrecking ball to the old ones?

Also given that intel still isn't shipping any quantity or anything at 90nm I take the 65nm claims with a grain* of salt.

*the process size of said grain may vary

Re:Ouch!

[WinterSolstice]

So?

The plant in Dresden will actually work, producing actual chips. This bit from Intel is just vapor at this point.

Besides, Intel will have to re-tool, debug, and market anyway. It's not like AMD will be any different.

-WS

Translation:

[raehl]

"You can make a 80% to 100% price increase without any further improvements."

Re:Questions.

[henrygb]

This 2001 paper suggests that about three silicon atoms fit into an nanometre and that they could space "bumps" at 38 nanometres. But that was a long time ago.

65nm when 90nm isn't even out yet? hm

[David Jao]

Look, I am not a chip fabrication expert. I am merely a sideline observer. But based on my observations, Intel will probably not make it to 65nm in 2005.

My position is based on nothing more than simple counting:

• Intel achieved 250nm process technology (deschutes) in January 1998
• ... 180nm (coppermine) in October 1999, although availability was scarce until January.
• ... 130nm (northwood) in January 2002
• ... 90nm (prescott) is not out yet, although it is supposed to be out in fourth quarter 2003. I'm going to go out on a limb here and predict January 2004.

Their track record is clear: the average time between circuit size improvements is two years. Based on their history, 2005 would be a stretch, with the most likely release date falling somewhere in early 2006.

Ooops, for got to square properly

[FuzzyDaddy]

1 square meter = 1 meter*1 meter = (10^6 micron * 10^6 micron) = 10^12 square microns.

1 square meter is NOT 10^6 square microns.

But bonus points for being the first one to make this mistake in this thread, someone always does.