Intel To Produce 65-Nanometer Chips In 2005

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Comments

Re:Reduce Power?

[addaon]

The relative importance of leakage increases at smaller geometries, but for all geometries on the near horizon, the increase isn't enough to outweigh the decrease in 'normal' (switching) power usage. This will probably change around 40 nm, but at 65 nm we're still making serious improvements.

Ooops, for got to square properly

[FuzzyDaddy]

1 square meter = 1 meter*1 meter = (10^6 micron * 10^6 micron) = 10^12 square microns.

1 square meter is NOT 10^6 square microns.

But bonus points for being the first one to make this mistake in this thread, someone always does.