Intel To Produce 65-Nanometer Chips In 2005

Ridgelift writes "In keeping with Moore's Law, Intel will begin mass-producing chips using 65-nanometer process technology in 2005, according to a ZDNet article (additional coverage at EE Times and The Inquirer). Intel recently produced a Static Random Access Memory (SRAM) cell at 0.57 square microns, in comparison to 90-nanometer process measuring 1 square micron. "You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Comments

Intel culture

[BiggerIsBetter]

What a beautifully telling Intel quote that is, "You can get a 40 to 50 percent increase in clock speed with no further improvements". Just keep ramping it up boys.

Reduce Power?

[brandido]

According to the article,

Reducing the size of the chip improves performance, reduces costs and can potentially cut energy consumption. In a nutshell, electrons have a shorter commute in 65-nanometer chips, so performance goes up. The gate length--the distance electrons travel to get from the source to the drain on a transistor and thereby flip the transistor on--drops from 50 nanometers to 35 nanometers in 65-nanometer chips.

However, it was my understanding that power consumption will often go up with smaller geometries as leakage current increases with the smaller gaters. Can anyone elaborate on this?

Re:Reduce Power?

[John Courtland]

There's all sorts of problems when you get that small and fast. EMF interference, gate jumping, electron migration. The thing basically is a small radio transmitter, and starts causing itself problems just by running so fast. They need to really start designing more intelligently, unlike (as a previous poster stated) "ramping it up".

Re:Reduce Power?

[addaon]

The relative importance of leakage increases at smaller geometries, but for all geometries on the near horizon, the increase isn't enough to outweigh the decrease in 'normal' (switching) power usage. This will probably change around 40 nm, but at 65 nm we're still making serious improvements.

Moore's Law

[worst_name_ever]

In keeping with Moore's Law

Well, more like "keeping Moore's Law a self-fulfilling prediction for yet another generation of processors". ;)

I have no doubt they can do it.....

[Selecter]

But it seems to me to be rather premature announcement, supposing these chips will be out when Intel says they will be. I think Intel is starting to feel the heat from quarters they didnt expect, like AMD and Apple via the good graces of IBM. Athlon 64 looks like a winner and so does the IBM made G5. IBM and AMD both have great looking roadmaps for the future.

This smells like a another smear piece by Intel to me, kinda like paper launching the P4 Emergency Edition on AMD's rollout day for the Athlon 64.

Boo. Hiss.

Re:I have no doubt they can do it.....

[Selecter]

I thinks it's premature to build a few test SDRAM cells and then magically announce they are going to build chips using that tech in possibly less than 1 year and 1 month. It's far more likely they will not meet that target, given the real hurdles of fully implementing that process to overcome. A few SDRAM cells does not a P5(6?) make.

Also, someone is not telling the truth.

"The 65-nanometer chips will not include the IBM-touted silicon-on-insulator technology, either. "We have not seen any significant performance advantages with SOI," Bohr said."

Well, who is it? IBM and AMD are going with it. Who's wrong, Intel or IBM/AMD? I'd like to know.

40 to 50 percent increase?

[Anonymous Coward]

"You can get a 40 to 50 percent increase in clock speed with no further improvements" says Intel director Mark Bohr."

Yeah, I get those "40 to 50 percent increase" emails all the time...I've been deleting them as fast as they come in.

Ohhhhhh...wait.... He said CLOCK, not COCK
nevermind :-)
TDz.

Re:PC Toaster

[jon787]

what is scarier, you thought of it, or somebody did it

Re:Moore's "Law"?

[taradfong]

Similarly, "Murphy's Law" was supposed to be called "Murphy's Axiom" but something got screwed up.

65nm when 90nm isn't even out yet? hm

[David Jao]

Look, I am not a chip fabrication expert. I am merely a sideline observer. But based on my observations, Intel will probably not make it to 65nm in 2005.

My position is based on nothing more than simple counting:

• Intel achieved 250nm process technology (deschutes) in January 1998
• ... 180nm (coppermine) in October 1999, although availability was scarce until January.
• ... 130nm (northwood) in January 2002
• ... 90nm (prescott) is not out yet, although it is supposed to be out in fourth quarter 2003. I'm going to go out on a limb here and predict January 2004.

Their track record is clear: the average time between circuit size improvements is two years. Based on their history, 2005 would be a stretch, with the most likely release date falling somewhere in early 2006.

Ooops, for got to square properly

[FuzzyDaddy]

1 square meter = 1 meter*1 meter = (10^6 micron * 10^6 micron) = 10^12 square microns.

1 square meter is NOT 10^6 square microns.

But bonus points for being the first one to make this mistake in this thread, someone always does.