Strained Silicon Chips From Intel

Quirk writes "NewScientist is reporting... "Intel has taken the wraps off a secret technique it is using'Strained silicon' chips to increase the speed of its Pentium and Centrino chips. The technique boosts the rate at which transistors switch, without having to make them smaller.""

Comments

Re:Since when is Strained Silicon Secret?

[Dreadlord]

true, I was going to post something similar, here is the link to IBM's research about Strained Silicon.
I first thought it was the submitter's mistake, but actually the story is taked off the article.
Maybe someone can shed some light here.

Re:Mechanical Stress

[mercuryresearch]

I spoke with Intel about this in the spring.

Apparently the strained silicon technology came about due to research related to mechanical stress problems they were encountering across the entire chip -- so it already was an issue. Their research solved the mechanical stress problem, and they later realized by intentionally localizing the effect they could basically place the strain at individual transistors to improve performance.

Because the effect is localized and controlled it's no longer an issue of concern, AFAIK.

Heat sinks, etc, shouldn't alter the strain at the transistor level. Remember, we are talking about this at the atomic level, so any macro-level strain like a heat sink would have to be pretty substantial to work its way down into the crystal lattice structure to the point of affecting performance. (Sort of humorous if it did, though, as it would imply microprocessors would go faster if you squeezed them. In reality Intel is actually stretching the size of the normal silicon lattice structure, so heat sink stress (compression) would actually be working against you, but it's also occuring in the wrong axis (the lattice stretching is 2D X-Y, not Z-axis.)

Several technologies...

[NerveGas]

There are several new technologies that either are speeding up chips, or will speed up chips, and the best part is that they'll all work together.

For some time, SOI (silicon-on-insulator) has been helping chip manufacturers squeeze out extra performance. And the straining of the silicon lattice (strained silicon) helps as well. And you can combine them into SSOI, strained-silicon-on-insulator.

Well, there's also one other technology that's been developed, called "fully depleted silicon". And guess what - it should/will be possible to make fully-depleted, strained silicon-on-insulator chips. (FDSSOI?)

Between moving to 90 nm, then 65nm, and then further, as well as integrating high-K dialectrics and fully-depleted, strained silicon-on-insulator manufacturing technologies, we've still got a lot of headroom to keep cranking out faster and faster processors. Moore's law has still got a long time to live. And that's even if we don't make any new breakthroughs, but my guess is that the chip makers will continue to pull aces out of their sleeves, so to speak.

steve