Slashdot Mirror
First Ever Nanotube Transistors On A Circuit
btsdev writes "Researchers at the University of California at Berkeley and Stanford University have developed the first ever integrated silicon circuit with nanotube technology. According to the article on UC Berkeley's site, this brings researchers one step closer to developing memory chips with carbon nanotubes - chips that could hold approximately 10,000 times more data than those we have today."
Ummmm. There is a pretty serious problem with heat dissapation and CARBON nanotubes Like this report shows
Isnt this going to cause a pretty serious problem in integrating nanotube technology into electronics ?
Obviously you're not familiar with Dr. Noe Huntley's articles... http://www.users.globalnet.co.uk/~noelh/physmob.ht m
The inevitability of artificial, perfect diamond has DeBeers white in the face. It also provides more fuel for the The Law of Accelerating Returns (rather than "Moore's Law").
--
Power to the Peaceful
How many bit CPUs will we need to address 1,280,000MB of RAM?
41.
In 1995, there was alot of talk about a glass cube that can store a terabyte of data. This technology was expected to be around the market by 2005. Where is it now?
Exactly. Like 90% of the great technical innovations they either don't make it for political reasons. Or heavily delayed for an eternity. Scary part is, Doom III will probably come out after this stuff.
"Ok, if you have 10,000 more the space, it all disappears when you power off right?"
Actually, no. The basic technology from the last story (can't find it now - slashdot's search seems disabled now) implied that the memory would not require constant charge, but would instead be based on van-der-waals effect on many nanotubes to make up one bit. It's not the most efficient method - it's just much more data-dense than current methods.
Ryan Fenton
sigh. when the g4 was introduced, the united states defined "supercomputers" or "high performance computers" for the purpose of export as any machine that could do 2000 MTOPS (million theoretical operations per second).
any machine that met this definition was under strict export control to "tier 3" countries (n. korea, iran, pretty much all of s. america &c.). hence the "supercomputer" appellation from jobs & co.
now the export control for computers has been raised to 6500 MTOPS - so iranians can merrily get their g5's.
2 1337 4 u!
For a RISC cpu, each word contains an instruction. The address is embeded inside that instruction. With 64bits, this leaves you with a 22bit command and a 42 bit address. The maximum memory addressed is then 2^42 bytes - or four terabytes.
The advantage of doing it this way is that the entire memory space can be addressed in a single instruction - no complex addressing schemes are required. Simple is good.
You don't belive me - check the literature on the G5, located here. (See page 7)
Its something to note that while many chips can have 64 bit pointers, the chip does not necessarily support 64 address lines. For example, from the Athlon 64 FX Datasheet found here, we know that the Athlon 64 FX has 40 physical address lines, Granted, that's still a Terrabyte of physical address space, but, its nowhere near the numbers you quote.
Mind you, the originaly 68000 was like this, with only 24 physical address lines, as were the 80486SLC's with only 24 physical address lines, despite being 32bit internally. Oh, and I believe MIPS arches have 30 address lines because they do not support non word-aligned read/writes, but that may or may not be true.
Oh, another thing, the Athlon 64 does clock in 64 or 128 bits per read/write cycle, so even if it uses the physical address lines for the high bits (most likely) its still not the full 64 bit address space.
fnord.
My course in VLSI design was many, many years in the past, but what I do remember is that early integrated circuits used metal gates in the fabrication process. That process was later abandoned in favor of polysilicon because poly was much easier to work with at smaller feature sizes (I'm a bit foggy on this one). Gee, so now we're going back to metal gate processes, and we'll have real metal-oxide-semiconductor field effect transistors again?
If this is becoming easier to do at deep submicron level, I suppose processes for making deep submicron feature-sized Gallium-Arsenide MESFET's also got easier? Now wouldn't we just love to have such GaAs chips on our desktops... (I do know I'm forgetting another difficulty in working with GaAs, anyone care to remind me why GaAs is not as common as silicon today?)
litigious bastards
suck it sco!
>anyone care to remind me why GaAs is not as common as silicon today?
price. silicon is dirt cheap, gaAs not.
At least, they're not laying claim to it (though you can bet they would like to). Their more modest (!) goal is to characterize the fabrication process in hopes of achieving higher yields of semiconducting (vs. metallic) CNTs.
There will definitely be a few problems with productization; molybdenum's not something you want to get anywhere near a commercial fab, and that big blob of CNT growth catalyst is a bit of a disaster. But this looks like a very nice bit of engineering.
...not in any computationally useful sense, anyway. Now, I'm not knocking this research, because it's a great way to make a bunch of nanotubes and examine them quickly (much faster than the usual process of making nanotubes, decorating a surface with them, hoping some of them line up with the traces you've deposited, etc.) -- but the fact remains that this is still basically an aleatoric process. You grow a bunch of nanotubes, and you know that some of them are going to be your nice metallic armchair nanotubes, some are going to be your nice semiconducting zigzags, and some are going to be junk. We don't have any way of controlling what type of nanotube we want to grow yet, nor do we have any way of getting yields high enough to make a traditional microprocessor. Right now, maybe 10 percent of the "transistors" you make out of molecules actually act like transistors. Since your Athlon is junk if even a few of its transistors or interconnects go bye-bye, and even Teramac didn't try to run with 90 percent of its transistors failed, it is clear that nanotubes for desktop-type computation are way out on the horizon.