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Linux Shootout: Opteron 150 vs. Xeon 3.6GHz Nocona
danalien writes "Anandtech with their previous review have stirred up a bit of controversy, and they've released their follow-up review where they pit AMD's Opteron 150 vs Intel's Xeon 3.6 Nocona (on linux)."
No message here. Oh, did you know that an Athlon64 3000+ is within 2fps of a P4 3.4 Extreme Edition in Doom 3?
Look up the prices for those two items.
It's good to see benchmarks between processors in the same family, but is there anywhere that regularly tests CPUs across families? x86, PPC, Sparc, VIA etc. I'd like to see comparisons like that to see how various architectures strengths & weaknesses stack up
There's been some controversy about benchmarks being set up in favor of Intel, thus allowing it's processors - even having lower amount of MHz - to win most.
But I've seen some computers which, having only switched from AMD to comparable (in clock frequency) Intel processor, got some boost in speed. Especially in games. And I've seen some changing from Intel to AMD, suffering loss of speed - mainly in games.
I don't know if recent games (I've seen these effects mainly with Neverwinter Nights) are compiled with optimization for Intel line of 686, but that's the fact - AMD performed worse. In these particular computers, with some particular games of course.
I submitted this story an hour or two ago, but thinking about it it will be rejected just like everything else, and then pop up under someone else's name.
so what the hell.
Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates
Summary
This document details the procedure for performing microcode updates on the AMD K8 processors. It also gives background information on the K8 microcode design and provides information on altering the microcode and loading the altered update for those who are interested in microcode hacking.
Source code is included for a simple Linux microcode update driver for those who want to update their K8's microcode without waiting for the motherboard vendor to add it to the BIOS. The latest microcode update blocks are included in the driver.
Background
Modern x86 microprocessors from Intel and AMD contain a feature known as "microcode update", or as the vendors prefer to call it, "BIOS update". Essentially the processor can reconfigure parts of its own hardware to fix bugs ("errata") in the silicon that would normally require a recall.
This is done by loading a block of "patch data" created by the CPU vendor into the processor using special control registers. Microcode updates essentially override hardware features with sequences of the internal RISC-like micro-ops (uops) actually executed by the processor. They can also replace the implementations of microcoded instructions already handled by hard-wired sequences in an on-die microcode ROM.
AMD's U.S. Patent 6438664 ("Microcode patch device and method for patching microcode using match registers and patch routines") goes into substantial detail on this.
Typically microcode update blocks are stored in the BIOS flash ROM and loaded into the processor as the system boots. They can also be loaded by the operating system; for instance, Linux contains a microcode device driver for Intel chips.
AMD recently released a "BIOS fix" to motherboard makers to address Errata 109, in which REP MOVS instructions caused subsequent instructions to be skipped under specific pipeline conditions.
Previously it was not clear if and how AMD even supported microcode updates in the K8 family until this announcement. After analyzing a number of BIOS images, it appears that AMD has secretly used the microcode update facility on several occasions over the past few years, but obviously avoided publicly disclosing that it actually had bugs patchable in this manner.
Early K7 (Athlon) cores initially supported microcode updates as well, until ironically the microcode update mechanism itself was found to be broken and subsequently listed as an errata!
The following sections describe the microcode update procedure, obtained by clean room reverse engineering various vendors' BIOS code. The actual microcode update blocks are embedded in the BIOS image; the most recent updates (created June 2004) have been included in the Linux driver source code attached to this description.
Microcode Update Procedure
The update procedure expects the 64-bit virtual address of the update data, including the 64 byte header, to be in edx:eax:
edx = high 32 bits of 64-bit virtual address
eax = low 32 bits of 64-bit virtual address
ecx = 0xc0010020 (MSR to trigger update)
Execute wrmsr with these register values. If the address and update block data are valid, wrmsr completes successfully. Otherwise, a GP fault is taken.
The microcode does not appear to update MSR 0x8B with the new update signature as it does on Intel processors, despite the fact that some BIOS code I have analyzed does seem to check this field. It is possible the MSR is only updated under certain conditions, for instance when microcode is loaded before initializing the cache controller. Nonetheless, as we shall see below, the processor is clearly doing something internally when it claims to accept an update in this manner.
The update generally takes around 5500 clock
http://slashdot.org/~GuyFawkes/journal
I recently installed Fedora 2 on a dual Opteron 248 system (Sun V20Z) and was amazed at the sheer grunt of the thing. Why anyone would even consider buying a Xeon just amazes me. I ran one of my own integer and memory heavy benchmark programs (single threaded) against my Athlon XP 2200+ and a single Opteron processor was 3x faster than the XP for only 400Mhz higher clock speed. These things are amazing, Intel should be crapping themselves and I am sure they would be if it wasn't for the cozy deal with Dell and the number of sites that have a Dell only policy. In a true free market they would be toast.
"I have the attention span of a strobe lit goldfish, please get to the point quickly!"
your argument is pretty fucking retarded. it is NOT always better to move away from a BUS architecture.
simple proof: consider an array of 486 processors connected by an ultra-fast, ultra-low-latency network.
long boring argument for idiots like you: suppose you have a single value in memory, called 'GO!!', it has the value 0 or 1. If it's ever set to 1, all the CPUs have to do some work and write an answer or something. If it's set to 0, the CPUs have to stay idle, otherwise the electricity man comes and shoots you.
On a Xeon (or any other bus) system: *THE INSTANT ANY CPU WRITES A ONE TO GO!!, ALL THE CPUS KNOW IT!! AND CAN START WORKING INSTANTLY!* No other messages need to be sent. Nothing. This is called "bus snooping" and you can only do it on, well, a bus, or other _shared_ communications medium.
On the Opteron architecture (we call this NUMA, or "point-to-point"), as soon as one CPU writes a value to the 'GO!!' area, well, that's _just the beginning_. It has to tell another CPU in the system that it just did that. etc etc.
Do you get it now?? When designing a NUMA system, you can choose _at which point_ you want to make things point-to-point, below which you want things to remain shared, so that tightly coupled (shared) data can be thrashed around efficiently, without blasting millions of messages here and there, saturating router buffers etc.
For example, the now-famous SGI Altix systems are point-to-point, just like Opterons, but only in two-CPU blocks, each of which has a shared (Itanium) bus. Even though this bus protocol explicitly supports up to 4 CPUs on the same bus. (this is unlike, say, HP's 4-CPU systems that as far as I'm aware have all 4 Itaniums on a bus, and only go point-to-point beyond that)
"As we can see above, the difference between the two CPUs seems exaggerated and difficult to trust."
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The opteron seems to trounce the Xeon in most of the tests. The tests where it doesn't win outright, it is barely edged out. And this is from an Intel processor that mere mortals can't even buy right now against an Opteron I can order today and have in my hands tomorrow. That doesn't bode well for Intel.
Given the wide performance delta in AMD's favour in the database tests in this uniprocessor setting, I can't wait to see how things stack up with dual or quad processors. I know what I'LL be using next time I need to spec a departmental or enterprise database box.
Cheers,
Actually, your information is out-of-date. The new Socket 939 Athlon 64's (both the + and FX series) feature a dual-channel memory controller for unregistered DDR SDRAM (this is one of the big reasons for introducing the new socket in the first place).
This still leaves me wondering why an Opteron 250 (2.4GHz, 1MB L2 cache) seems to so seriously outperform an Athlon 64 3500+ (2.2GHz, 512KB L2 cache).
It seems to me that AnandTech seems to be biased in Intel's favor for some odd reason. Either that, or that particular reviewer happens to be. Last week in their other review they said the Intel Xeon processor was way better - even when the results were about the same skewed in Intel's favor. Now that the results are skewed toward AMD the reviewer still refuses to see that the Opteron is a better processor, is available NOW, and is $250 cheaper than the Xeon-yet-to-be-released that they are comparing it too.
*Sigh* I've lost all faith in reviews by some of these hardware sites lately - they seem to be getting paid by someone to make invalid conclusions (or none at all) from fairly conclusive data.
"To strive, to seek, to find, and not to yield." - Tennyson
How about profiling bytecode interpreters for the new breed 64 bit processors.
Both Sun (the original innovators) and now Microsoft are putting their money on their bytecode (rather than binary) executables to try and avoid the whole backwards compatibilty problems when moving architectures. To get to grips with how important this is - Microsoft has only just recently managed to escape from the 16 bit code hell that it lived in for years (need proof - check out the Win16Lock you needed to get access to the video memory in DirectX).
That said, I can't imagine that many (someone might enlighten us here) performance benchmarks that a 64 bit bytecode interpreter could do better in when compared to its 32 bit smaller brother.
What would be interesting here would be to see how Javas bytecode and CIL scale to 64 bit. My first guess would be that Java should scale better (with Suns heritage of 64 bit platforms) but I wouldn't be surprised if MSFT weren't too far behind, as they were always keeping their eye on this test when designing the CIL. This would also be a good chance for the Mono project to try a "ours is better than yours" benchmark for their interpreterrs.
[ Monday is a terrible way to spend one seventh of your life. ]
240 = 1.4GHz, £145
242 = 1.6GHz, +£15 / +14% faster clock
244 = 1.8GHz, +£90 / +28%
246 = 2.0GHz, +£190 / +43%
248 = 2.2GHz, +£345 / +57%
250 = 2.4GHz, +£465 / + 71%
First step's a no-brainer; next one isn't too bad, after that you're hitting significant diminishing returns, with each 200MHz gap being a smaller proportion of the total clock, not to mention other things becoming more likely to bottleneck (IO; memory bandwidth, disk latency, network, PCI bus, etc).
Core differences are going to be minimal, and hypertransport's remained at 800MHz across the S940 range afaik, so the clocks *should* be a pretty accurate upper bound on the performance differences within each range.
We have been benchmarking several loaner boxes at work to determine what will be our next purchases for our compute farm. We do primarily ASIC and FPGA design, simulation and verification. We have been in dire need of >4GB boxes, and until just recently, we had been forced to run on Solaris machine to get 8GB.
The day of the Opteron, however, has come at last:
All these were run with stock tools in 32-bit mode, no fancy compiler optimizations. These are the same programs that we run on 2GHz P4s.
Agilent 3070 VCL vector conversion Perl program (which I wrote, this is very typical of the Perl programs we run to process large vector files - the benchmark only times data processing in memory, no file IO on read/write):
Sun Blade-1000 750MHz: 103.08 sec
P4 3.06GHz: 36.93 sec
Opt 148 (2.2GHz): 27.01 sec
Quad Opt 848: 27.42 sec
Quad Xeon64 (3.6GHz): 31.17 sec
Modelsim 5.8c simulation of LogicBIST simulation on 50K Flop ASIC:
P4 3.06GHz: 5955 sec
Opt 148: 3798 sec
4x Opt 848: 5985 sec (See note below)
4x Xeon64: 4858 sec
Mentor Flextest fault grading using make -j1, -j2 and -j4 (parallel runs, results combined in later step that is not benchmarked):
Sun Blade-1000: 7362 sec(-j1)
P4 3.06GHz: 2188 sec(-j1)
Dual P4 3.06GHz: 2189 sec/1333 sec (j2)
Opt 2.2GHz 128: 1493 sec
4x Opt 2.2GHz 848: 1562 sec(j1)/ 779 sec(j2)/ 393 sec (j4)
4x Xeon64 3.6GHz: 1465 sec(j1)/796 sec(j2)/ 879 sec(j4)
Mentor LbistArchitect on 50K ASIC:
Sun Blade-1000: 15698 sec
P4 3.06GHz: 3877 sec
Opt 148: 2845 sec
4x Opt 848: 3534 sec (See note below)
4x Xeon-64 3.6GHz: 2604 sec
Note - the poor performance of the quad opteron box was done on RedHat Enterprise Linux 3 AS-6, and I noticed that the SMP kernel did NOT have CONFIG_K8_NUMA set to y, so it's not fair to judge those numbers until we get a new kernel with ccNUMA support. I have run synthetic benchmarks on them too, and the memory performance on the Quad Opteron was indeed hurt by the lack of CONFIG_K8_NUMA in the linux kernel.
Clearly though, the HyperTransport makes the Quad Opteron box scale very well, whereas the Quad Xeon box choked on 4 threads, probably beacuse the memory bus became saturated and the processors starved for data.
Also, any serious optimizations need to use gcc-3.4.1 - which has specific optimizations for both Opteron and Nocona cores. gcc-3.4.0 does not have specific optimizations for Nocona ("Xeon64") cores. gcc-3.x does not have specific optimizations for Opteron.
Anyway, our decision has been made - we are buying Opteron 150s for all our new compute farm boxes.