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Linux Shootout: Opteron 150 vs. Xeon 3.6GHz Nocona
danalien writes "Anandtech with their previous review have stirred up a bit of controversy, and they've released their follow-up review where they pit AMD's Opteron 150 vs Intel's Xeon 3.6 Nocona (on linux)."
No message here. Oh, did you know that an Athlon64 3000+ is within 2fps of a P4 3.4 Extreme Edition in Doom 3?
Look up the prices for those two items.
To be able to show the real potential of the Opteron, you need to have more than one processor.
This lets you take advantage of the on-die memory controller, by letting each processor do it's own memory work, rather than making the Northbrige do all the work.
If you want to use a single processor, you might as well use an FX-Whatever, since they are just an Opteron without MP capability and only one HT bus.
Athlon 64 is the name used for the desktop line, and Opteron is the name used for the server/workstation processors.
It's good to see benchmarks between processors in the same family, but is there anywhere that regularly tests CPUs across families? x86, PPC, Sparc, VIA etc. I'd like to see comparisons like that to see how various architectures strengths & weaknesses stack up
I submitted this story an hour or two ago, but thinking about it it will be rejected just like everything else, and then pop up under someone else's name.
so what the hell.
Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates
Summary
This document details the procedure for performing microcode updates on the AMD K8 processors. It also gives background information on the K8 microcode design and provides information on altering the microcode and loading the altered update for those who are interested in microcode hacking.
Source code is included for a simple Linux microcode update driver for those who want to update their K8's microcode without waiting for the motherboard vendor to add it to the BIOS. The latest microcode update blocks are included in the driver.
Background
Modern x86 microprocessors from Intel and AMD contain a feature known as "microcode update", or as the vendors prefer to call it, "BIOS update". Essentially the processor can reconfigure parts of its own hardware to fix bugs ("errata") in the silicon that would normally require a recall.
This is done by loading a block of "patch data" created by the CPU vendor into the processor using special control registers. Microcode updates essentially override hardware features with sequences of the internal RISC-like micro-ops (uops) actually executed by the processor. They can also replace the implementations of microcoded instructions already handled by hard-wired sequences in an on-die microcode ROM.
AMD's U.S. Patent 6438664 ("Microcode patch device and method for patching microcode using match registers and patch routines") goes into substantial detail on this.
Typically microcode update blocks are stored in the BIOS flash ROM and loaded into the processor as the system boots. They can also be loaded by the operating system; for instance, Linux contains a microcode device driver for Intel chips.
AMD recently released a "BIOS fix" to motherboard makers to address Errata 109, in which REP MOVS instructions caused subsequent instructions to be skipped under specific pipeline conditions.
Previously it was not clear if and how AMD even supported microcode updates in the K8 family until this announcement. After analyzing a number of BIOS images, it appears that AMD has secretly used the microcode update facility on several occasions over the past few years, but obviously avoided publicly disclosing that it actually had bugs patchable in this manner.
Early K7 (Athlon) cores initially supported microcode updates as well, until ironically the microcode update mechanism itself was found to be broken and subsequently listed as an errata!
The following sections describe the microcode update procedure, obtained by clean room reverse engineering various vendors' BIOS code. The actual microcode update blocks are embedded in the BIOS image; the most recent updates (created June 2004) have been included in the Linux driver source code attached to this description.
Microcode Update Procedure
The update procedure expects the 64-bit virtual address of the update data, including the 64 byte header, to be in edx:eax:
edx = high 32 bits of 64-bit virtual address
eax = low 32 bits of 64-bit virtual address
ecx = 0xc0010020 (MSR to trigger update)
Execute wrmsr with these register values. If the address and update block data are valid, wrmsr completes successfully. Otherwise, a GP fault is taken.
The microcode does not appear to update MSR 0x8B with the new update signature as it does on Intel processors, despite the fact that some BIOS code I have analyzed does seem to check this field. It is possible the MSR is only updated under certain conditions, for instance when microcode is loaded before initializing the cache controller. Nonetheless, as we shall see below, the processor is clearly doing something internally when it claims to accept an update in this manner.
The update generally takes around 5500 clock
http://slashdot.org/~GuyFawkes/journal
I recently installed Fedora 2 on a dual Opteron 248 system (Sun V20Z) and was amazed at the sheer grunt of the thing. Why anyone would even consider buying a Xeon just amazes me. I ran one of my own integer and memory heavy benchmark programs (single threaded) against my Athlon XP 2200+ and a single Opteron processor was 3x faster than the XP for only 400Mhz higher clock speed. These things are amazing, Intel should be crapping themselves and I am sure they would be if it wasn't for the cozy deal with Dell and the number of sites that have a Dell only policy. In a true free market they would be toast.
"I have the attention span of a strobe lit goldfish, please get to the point quickly!"
Analogies don't equal equalities, they are merely somewhat analogous.
After all is said and done it became difficult (nearly impossible?) to justify the Xeon processor in a UP configuration over the Opteron 150,
Huh? Here are some numbers:
- POV-Ray 3.50c: Opteron is 40% faster
- Crafty v19.15: Opteron is 70% faster
- TSCP: 10% faster
- PostgresSQL test-insert and test-select: Opteron takes 60% of the time it takes Xeon
- MySQL test-insert: Opteron takes 80% of the time it takes Xeon.
In almost every benchmark, where proper optimizations are used (and why shouldn't they be? Who in his/her right mind would not use proper optimizations??), the Opteron destroys the Xeon.There are older dual and quad Opteron vs Xeon reviews around.
Humorously, the also say this:
Now we know that the Nocona is here, and it's getting slaughtered at the Altar of The Opteron.
Belief is the currency of delusion.
As hyperthreading cuts the L2 cache in HALF, it should be disabled before doing any of these benchmarks. Hyperthreading only seems to improve the multithreading ability. These benchmarks being run on a single process are not realistic.
Actually, your information is out-of-date. The new Socket 939 Athlon 64's (both the + and FX series) feature a dual-channel memory controller for unregistered DDR SDRAM (this is one of the big reasons for introducing the new socket in the first place).
This still leaves me wondering why an Opteron 250 (2.4GHz, 1MB L2 cache) seems to so seriously outperform an Athlon 64 3500+ (2.2GHz, 512KB L2 cache).
This still leaves me wondering why an Opteron 250 (2.4GHz, 1MB L2 cache) seems to so seriously outperform an Athlon 64 3500+ (2.2GHz, 512KB L2 cache).
When people says that the first article was bad, it's because it was really bad: 64-bit binaries for Intel vs. 32-bit binaries for AMD, copy&pasted benchmark results from previous 32-bit benchmarks, tests (PI digit computation) that measured the libc optimization instead of the actual benchmark (when removing the printf() it got about a 10x boost). People on aceshardware forums were posting TSCP scores about 2x what Anandtech got, on the same processor. So the A64 3500+ scores you saw in that article are trash. Forget them.
How about profiling bytecode interpreters for the new breed 64 bit processors.
Both Sun (the original innovators) and now Microsoft are putting their money on their bytecode (rather than binary) executables to try and avoid the whole backwards compatibilty problems when moving architectures. To get to grips with how important this is - Microsoft has only just recently managed to escape from the 16 bit code hell that it lived in for years (need proof - check out the Win16Lock you needed to get access to the video memory in DirectX).
That said, I can't imagine that many (someone might enlighten us here) performance benchmarks that a 64 bit bytecode interpreter could do better in when compared to its 32 bit smaller brother.
What would be interesting here would be to see how Javas bytecode and CIL scale to 64 bit. My first guess would be that Java should scale better (with Suns heritage of 64 bit platforms) but I wouldn't be surprised if MSFT weren't too far behind, as they were always keeping their eye on this test when designing the CIL. This would also be a good chance for the Mono project to try a "ours is better than yours" benchmark for their interpreterrs.
[ Monday is a terrible way to spend one seventh of your life. ]
240 = 1.4GHz, £145
242 = 1.6GHz, +£15 / +14% faster clock
244 = 1.8GHz, +£90 / +28%
246 = 2.0GHz, +£190 / +43%
248 = 2.2GHz, +£345 / +57%
250 = 2.4GHz, +£465 / + 71%
First step's a no-brainer; next one isn't too bad, after that you're hitting significant diminishing returns, with each 200MHz gap being a smaller proportion of the total clock, not to mention other things becoming more likely to bottleneck (IO; memory bandwidth, disk latency, network, PCI bus, etc).
Core differences are going to be minimal, and hypertransport's remained at 800MHz across the S940 range afaik, so the clocks *should* be a pretty accurate upper bound on the performance differences within each range.