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Intel Shrinks Transistor Size By 30%
pinkUZI writes "Intel will announce that it has crammed 500 million transistors on to a single memory chip, shrinking them in size by 30%. " The tech details are sadly lacking in the article - but I'm sure those will follow. Indeed, the Yahoo piece gives the details that "...has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers."
You're thinking DRAM, with one transister per bit, but slow (plus it needs refreshing every 60msec or so). Static RAM is mucho faster, with 4 to 8 transistors per bit.
Also, your math is in error. 500M transistors for 70 Mbits works out to 7 transistors per bit. I'm guessing the visible portion of the chip will be 64Mbits and 6 transistors/bit, with most the rest of the transistors allocated as spares. When you make a chip that big, you can boost yield by making spare blocks of memory that during manufacturing can be substituted for bad areas on the chip.
--- Often in error; never in doubt!
Well, sorta.
Smaller transistors generally require less power to operate because they can (actually, must) be operated at a lower voltage. Dynamic (swtiching) power varies with the square of the voltage, so dropping the voltage a little makes the power go down a lot.
But that's just switching power.
As gate sizes shrink, previously negligible leakage (static) power increases. A lot. Now it's no longer negligible at the 90nm and 65nm process steps. In fact, it's getting very close to the same order of magnitude as switching power.
That's a problem because you can limit dynamic power by switching more slowly, or not switching certain transistors at all (think mobile CPU speed throttling.) But leakage power is consumed even if the CPU clock isn't ticking. If voltage is applied to the chip, power leaks.
everything in moderation
"Reduced transistor size by 30%" is an odd way to announce moving from a 90nm to a 65nm process.
Just to help avoid any confusion here, this is not some new clever transistor design or something. It's just another incremental step in process size reduction. It happens every few years. And it's not just Intel -- I know IBM and NEC are doing 65nm right now as well. I suspect TSMC and UMC are also, though I'm not sure (I know UMC had problems in 90nm that they're still fighting with . . )
everything in moderation
Your post is accurate and informative in general, but there's one nit I must pick:
But as a rule of thumb, the closer you bunch up the transistors, the higher the electrical leakage.
It's not the bunching up (density) of the transistors that increases leakage current (static power consumption,) it's the gate size. Narrower gates are less good at being the perfect insulators they should be. The thinner dielectric allows more leakage current, and can even break completely if the voltage is too high, which is why smaller-geometry processes often allow (or require) lower operating voltages, which helps reduce synamic (switching) power.
Of course, it's the shrinking of the gates (and the rest of the transistors) that allows them to be bumched up more (placed in higher density,) so maybe you meant it that way . . .
everything in moderation
With all due respect, I think you're confused. For the same operating voltage, dynamic power does not decrease with decreasing gate size/transitor size.
P=1/2*Ceff*V^2*f*N+Q*V*f*N+I1*V
where P is power consumption, Ceff is effective load capacitance, f is frequency, V is source voltage, N is signal switching coefficient, Q is charge due to through-type current, and I1 is leakage current.
While the actual gate capacitance driven may be reduced by virtue of it's smaller size, the effective capacitance (that "seen" by the driver) stays roughly the same, or may even get higher from parasitic capacitance. The only thing sure to change is the leakage current, which will increase as gates shrink.
Maybe this will help you understand.
everything in moderation
There are three components to leakage current in DSM CMOS devices. From here in order of magnitude: (1) source-drain junction leakage current (2) gate-direct tunneling leakage, and (3) sub-threshold leakage current.
And while neither of us pointed out all three, the fact remains that it's not the "bunching up" of the transistors that increases leakage, it's the gate and transistor sizes (which tend to scale together.) Which was the point I was trying to make.
If you think gate leakage is negligible compared to sub-threshold leakage, you'd better tell the IEEE and all those people working on high-K gate dielectrics.
everything in moderation