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AMD to Demo '8-socket' Dual-Core Opteron System
flynn_nrg writes "AMD will make the first public demonstration of a system built out of its dual-core processors today, the result of a strategy first made public almost a year ago. Two-core Opteron chips aren't due to ship until the middle of 2005, but AMD will have four of parts running inside an HP ProLiant DL585 server at its Austin plant later today."
but AMD will have four of parts running inside an HP ProLiant DL585 server at its Austin plant later today.
Does this mean HP is offically ditching the Itanium2? If so, strange move, albeit likely a smart one...
From what has been published prior, the maximum number of coherent HyperTransport links in one Socket 940 interface is 3 and the number of logical processors has been limited to 8 to keep cache snooping traffic managable. Because each dual core chip will have 2 independent caches, the coherency traffic will increase regardless of whether external dual cores are addressed as single HT units. Will this result in either: a) reduction of sockets for general-purpose servers to 4 or b) entirely new ccNUMA protocols being developed from previous generation Opterons?
OS loaders and schedulers can help keep chatty processes allocated to the right mem/processor, but something more has to be said about hardware-level coherency standards. The X-box was fast and efficient largely because its CPU used the video RAM natively, but PCs still have to slog data over the slow and non-coherent PCI, AGP, or PCI-Express busses between the CPUs and GPUs. An inter-vendor standard could bring PC CPU-GPU interaction efficiencies much higher. ccPCI-Express or HyperTransportx16 slots anyone?