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Analyst Doubts Intel's Dual-Core Demo
bakeacake writes "At Xbitlabs they have a article on the possibility that Intel's Dual core Preview at the IDF was not real. Would Intel sink this low?
"An analyst expressed doubts about demonstration of a 'real' dual-core microprocessor during an Intel's recent demonstration at Intel Developer Forum Fall 2004 in San Francisco, California. Insight's Nathan Brookwood believes that Intel was most likely to showcase a dual-processor system instead of a dual-core processor-based system during the show.""
It is two processors on a single die. It would be like having a dual processor system, but only needing a single socket to support it. Now add in Hyperthreading and it would appear to be a 4-way system. Many people are really excited about this, and it is definately a cool engineering feat.
Analyst Doubts Intel's Dual-Core Demonstration
Insight 64 Asks Whether Intel Has Desktop Dual-Core x86 Chip
by Anton Shilov
09/15/2004 | 01:55 PM
An analyst expressed doubts about demonstration of a "real" dual-core microprocessor during an Intel's recent demonstration at Intel Developer Forum Fall 2004 in San Francisco, California. Insight 64's Nathan Brookwood believes that Intel was most likely to showcase a dual-processor system instead of a dual-core processor-based system during the show.
At last week's Developer Forum, Intel demonstrated how its Digital Office vision might enable three workers in different locations to collaborate to solve a complicated problem. One of the workers ("Jason") had to juggle several compute-intensive tasks on his system, but the work flowed easily without the sorts of fits and starts that would plague many contemporary systems. At the conclusion of the demo, Bill Siu, the General Manager of Intel's Desktop Platforms Group, casually noted that "Jason was using a dual-core system on a 915 [i.e., Grantsdale] platform." When asked about it later during a Q&A session, Siu smiled coyly, and added only that the system used "an engineering prototype" of a dual core processor with "real silicon." This begs the question of what was really inside the box.
Nathan Brookwood, the principal analyst for Insight 64 believes there are three options of what Intel might demonstrate.
"The least likely scenario is that the demo used the first silicon samples of the dual-core product planned for release next year. Intel did demo the first silicon for its dual-core Itanium, and AMD had just demonstrated the first silicon for its Opteron processor the week prior to IDF. We believe that if Intel actually had achieved this milestone, it would have trumpeted the news far more loudly and widely; their awesome PR machine would have made sure everyone on the planet was aware of this accomplishment. So we discount this theory completely," Nathan Brookwood writes.
"It is a bit more likely that Intel crammed two of its current Pentium chips into a single package that could be plugged into the socket of a 915 motherboard. (This is known as a multi-chip package (MCP), and has been used for years in certain applications.) The standard P4 package measures about 30mm on a side, and could conceivably hold many discrete processors that only measure about 11mm on a side. Intel wouldn't do this just for an IDF demo, but the resulting MCP might be useful for evaluating dual-core platforms, especially if the initial dual-core design follows the scheme we outlined above. The system would certainly be consistent with Siu's claims of "dual core," "915," and "real silicon," Mr. Brookwood claims.
"It is even more likely that Intel merely designed a dual-processor motherboard around its 915 chipset. The 915 is normally used only in uniprocessor designs, but there is no reason why engineers inside Intel could not circumvent the restrictions that prevent Intel's customers from using the 915 in DP configurations. Designing a unique motherboard is clearly less expensive and takes less time than creating a multi-chip package, and the resulting system would come close to replicating the performance of the eventual dual-core product. Like the MCP scenario, this system would fit with Siu's claims of "dual core," "915," and "real silicon," Insight's 64 principal analyst concludes, leaving the readers to decide what exactly did Intel showcase.
The analyst notes that typical Intel-based SMP systems, such as those fuelled by Intel Xeon processors, have processor system bus bottleneck, as all the chips have to share one PSB, be it a 400MHz QPB for 4-way systems or 800MHz PSB for 2-way systems. It is believed that dual-core processors will also have to share the same bus, which may limit their performance, even though by the time dual-core desktop chips are available, Intel will also present 1066MHz infrastructure for such microprocessors.
Intel and AMD both showcased
Just a single CPU die with two CPUs on it. If the board can support it, it's like plugging two CPUs into one socket.
This is quite easy for AMD because of how bus logic works. The Athlon 64 series use an integrated memory controller, and normally, a second CPU uses the same connection to the system RAM that the first one does. (ie, one Hypertransport connection is shared, by design, between two CPUs.) So a dual-core CPU is trivially easy for them to implement, relatively speaking: they have space and heat issues, but all the architectural design work is done already.
Intel, on the other hand, hasn't designed this way. Instead, for years now, they have been totally focused around more and more clock speed. This has left AMD scrambling, becaus their chip designs get more work done per clock tick, so a 1600mhz AthlonXP will keep up quite nicely with a much higher-clocked P4. But consumers, thanks to Intel mostly, don't understand that, and so AMD came up with their numbering system instead. (they were lucky this worked, because at least one prior attempts at this, by Cyrix, failed utterly.)
Well, the worm is turning. Intel's aproach, that of "more megahertz, dammit!" is very rapidly running out of steam. They have been selling people for years on megahertz, and suddenly they're in the position where they can't increase megahertz easily anymore. This is a BIG deal for them; all those billions spent 'educating' consumers on something that wasn't true is coming back to bite them.
A dual-core Prescott will not be an easy thing, and will require substantial motherboard and chipset changes. And they have a fundamental bandwidth problem; P4s need very high memory bandwidth to really get good. The P4 didn't truly hit its stride until it went to a quad-pumped 200mhz bus... 800mhz effective RAM speed. At that point, the P4 architecture finally sits up and really starts singing. But doing a dual-core chip means that both CPUs have to share bandwidth, so to maintain performance, they'll have to go to a 1600mhz bus. That's not likely in the near future.
AMD is doing the exact same thing, but the A64 design is much less clockspeed- and bandwidth-intensive. It gets more work done per clock tick, doesn't hit the RAM as hard, and runs cooler. So it's a natural for dual-core. Forcing the P4 into that same mold, on the other hand, is a move of desperation by Intel. It won't work very well, but their crank-the-megahertz strategy suddenly isn't working AT ALL.
From what I can see, Intel is in trouble.
Umm....2 Chips on a Single die is dual core. So an overglorified dual cpu system on a single chip is a dual core chip. What else do you think a dual core chip is? Besides the Advantages of what you call shared cache are none. If essentially 2 (different) cores/chips share a single cache the performance could possibly be less than optimal. The only benefit of 2 cores sharing a single cache is to save on die size
I think the implication is that this was Dual die - single package rather than "Single die"
I think people often confuse the packaging of a chip and the "chip" itself (silicon) thinking that the plastic they see is the chip itself
-Em
RelevantElephants: A Somatic WebComic...
You were doing so good until this...
A dual-core Prescott will not be an easy thing, and will require substantial motherboard and chipset changes. And they have a fundamental bandwidth problem; P4s need very high memory bandwidth to really get good. The P4 didn't truly hit its stride until it went to a quad-pumped 200mhz bus... 800mhz effective RAM speed. At that point, the P4 architecture finally sits up and really starts singing. But doing a dual-core chip means that both CPUs have to share bandwidth, so to maintain performance, they'll have to go to a 1600mhz bus. That's not likely in the near future.
You even heard of Xeons dude? It's quite easy to predict how the Intel dual core chips will work...
The 9xx chipsets from Intel are all ready to go with dual CPU's (and cores) and the chips will be compatable with the current generation LGA775 socket.
Since dual cores will be sharing the bus in the same way the current Xeon CPUS share the bus, performace should be about the same....
And who the hell said that Intel will use dual core prescott's?? I think it's obvious that they will use Pentium M cores, with are also compatabile with the 9XX series chipsets from Intel
You are an AMD troll....
the motherboard is fairly jury-rigged to support it, and that says nothing about actually having a compiled O/S to run on the thing and take full advantage of it.
I'd say you're spot on. . . Seing that the northbridge, CPU, ans PCIe are on one board and the southbridge, PCI and other I/O controllers are on a seperate board. Of course as anyone in the CPU industry knows, that is a relatively common debug platform setup.
posting AC for hopefully obvious reasons.
oh and the OS is likely an internal OS derivitive of Linux .
Caches may make a minor difference, but AMD and Intel run the same instructions. To run them, they both have to fetch them, all of them. Because of this, AMD doesn't get more work done per memory access.
This appears to be some kind of sour graping about AMD being behind Intel on memory bandwidth for a long time.
The large your dataset is, the more bandwidth you need to process it at a given speed. Intel is just keeping up with the increasing size of datasets (programs+associated data). AMD needs to also.
AMDs chips are fine, Intels are also. Both do well on speed, power usage, etc. (I measure power usage on my PCs at the wall with a Kill-A-Watt). AMD is cheaper, that's nice. AMD also does 64-bit, that's nice. Intel will have to rectify the latter to remain competitive. But to say Intel is in trouble when P4 performs as well as AMD on 32-bit code, and they have P-M as a power-saving processor seems just like fanboyism to me.
Well, it most likely would have roughly double the transistors. Most of the difference is in the model it presents to the system. The system would need to be able to identify the single chip as two processors, kinda like hyperthreading. Unlike hyperthreading, this would really be two processors: double the number of registers, double the number of ALUs, double the cache, etc.
Network Security: It always comes down to a big guy with a gun.
It could have been a dual core or not. It doesn't matter, especially to the Marketing folks. Heck, I've made demos that my Marketing department has tried to pass off as real products- they like to call them "capabilities." Never mind that the manufacturing capability hadn't been worked out yet. I hate it when they say, "hmmm... maybe Mark can make 10k of them a month." :)
At least in Intel's case, there's the real possibility of actually having the part available when they say it will.
That said, I have an acquaintance (Hi, John!) who will never work for Intel again because fifteen+ years ago their Marketing department had done exactly that. At one conference they had a pretty little box on the table with a card that they said did something, while under the table they had the his, cobbled-together breadboard actually doing the work ("Ignore the man behind the curtain").
That's marketing. No big deal. That's why you wait for an actual released product. Anything else is vaporware.
You even heard of Xeons dude? It's quite easy to predict how the Intel dual core chips will work...
Dual socket Xeons get around their limited memory bandwith by loading up on cache. That's going to be much more difficult to with a dual core design since you're trying to get two cores on the same chip while keeping the die size managable.
Oracle doubles in price with a dual core chip too. I'm pretty certain Oracle has stated that for licensing purposes, a single chip with hyper threading counts as two chips. A dual core chip definately counts as two in that case.
-matt
The more transisters you put in a processor, the farther the signals have to travel, which reduces clock speed. Using 2 cores on one die improves locality of reference, which lets you use a higher clock speed.
Also, dual processor system (whether on the same die or not) perform better for multi-task applications (with both lightweight (threads) and heavyweight (no shared memory) tasks). UNIX like systems tend to see more benefit from this than VMS or Windows NT/2000/XP based systems, because they tend to have more processes.
Designing a more complex CPU is a harder task than simply joining two pre-existing designs, especially if your design has a built-in memory controller (as the Opteron does).
AMD did a dual core demo the week before. They opened the boxes, passed around sample chips, showed enlargements of the cores, etc.
Intel did their demo with a closed box, presumably in response to AMD. Only when asked if it was really dual core did they say it contained "real silicon".
Intel showed enlargements of their dual core Itanium chip along with their demo.
We can all shout and scream about how the netburst architecture doesn't work, but that doesn't make it true. 3.6 ghz p4's are FAST. Yes they run hot. Yes they don't get the same ops/mhz that short pipelines do, but they're doing okay. Intel still sells a butt-load of chips, and thats what they're in the business for.
Incidently, all that "sharing bandwidth" stuff is what the 2 cores on a dual-core opteron will do. It's also what ALL the 2-cpu xeons in the world are doing. Again, not the greatest plan ever, but it works well enough today. The shared bus on a dual-core prescott is no different from the shared bus on a dual-chip xeon today.
Intel is in trouble in that they might go from 93% market share to 85%. Look at the market today. Ultrasparc 4's are slower than Itanium, yet ia64 still isn't making real money. The G5 is a really fast processor, but apple has about 2% of the desktop market. Being the fastest processor THIS MONTH doesn't mean the world is going to come knocking. Being close and having a good marketing campaign is more important.
Uh, actually there are significant advantages to having a shared cache depending on the application. While it may not be too obvious, and its not true in all cases (ie 2 single core processors with 1MB L2 cache each will be a dual core with 1MB L2 in most all situations). In general however they will give the dual core chip a larger L2 cache to make up for the fight between the two processors to use (often including heuristics to ensure that one processor doesn't kick out all the other processors data from cache).
Where then do performance gains over simple dual core operation come from then? Well in many multithreaded applications there is a significant ammount of shared data. When processing this shared data only one copy needs to exist in the L2 cache. On top of that if one core is using the data (or used it recently) and the second processor needs to use it, the data exists in the first processors L1 cache (generally dual cores won't share L1 cache due to the necessity to locate L1 cache near the core of the processor for speed reasons. When this happens the 2nd processor must wait longer then normal for the first processor to update the L2 cache (cache coherence protocols and the fact that L1 cache is duplicated in L2 cache), but this is still an order of magnitude faster then a standard dual processor setup.
So there you have it, the advantages of a shared cache.
Phil
Given that the N64 is basically a permanently-uniprocessor SGI with a reality engine (not a RE/2 or anything) and slightly customized version of a Mips R4k core (R4600, IIRC), RDRAM and a cartridge port, that's pretty reasonable.
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
is indistinguishable from a rigged demo. Apologies to Asimov.
Er, don't you mean Clarke , as the AC also pointed out?
One of the many forks of the Jargon File also has an appropriate entry for this topic which also includes the version of the maxim that you used.