Philips, ARM Collaborate On Asynchronous CPU

Sean D. Solle writes "While not an actual off-the-shelf chip, Philips and ARM have announced a clockless ARM core using what they call "Handshake Technology." Read on for more about just what that means; according to this article, the asynchronous ARM chip has yet to be developed, but the same Philips subsidiary has applied similar technology to other microprocessors.

Sean D. Solle continues "Back in the early 1990's there was a lot of excitement (well, Acorn users got excited) about Prof. Steve Furber's asynchronous ARM research project, "Amulet". The idea is to let the CPU's component blocks run at their own rate, synchronising with each other only when needed. Like a normal RISC processor, one instruction typically takes one clock cycle; but in a clockless ARM, a cycle can take less time for different classes of instructions.

For example, a MOV instruction could finish before (and hence consume less power than) an ADD, even though they both execute in a single cycle. As well as energy-efficiency, running at effectively random frequencies reduces a chip's RFI emissions - handy if it's living in a cellphone or other wireless device."

Comments

Such a processor already exists

[philj]

See here. Developed by Steve Furber and his team at The University Of Manchester

Re:Such a processor already exists

[Anonymous Coward]

Yes, indeed they did. The article doesn't mention any collaboration between the teams, which seems strange because:

1) ARM like to licence CPU core design IP, as mentioned in a later thread.

2) One of the major upsides of asynchronous CPU design (said Prof. Furber on the Manc. Uni course) is that because the subcomponents of the CPU aren't nearly so tied to temperature, voltage and clock speed requirements (which directly affect flip-flop "set up" and "hold" time), the intellectual property invested in creating such a chip is far more reusable than any synchronous design.

So if this is (as I infer from the article) a clean-room implementation separate to the AMULET group's work, it's totally contrary to the ARM licensing model and duplicates a lot of effort. Which seems a shame.

Intresting implications

[luvirini]

If we see same thing applied to non ARM architectures, there a many strange things going to happen, as quite many things in current computers are based on the assumption that things have specific clock rates. Obviously things might get very intresting...

Re:Intresting implications

[pe1rxq]

Usually with these kind of asynchronous cpus the communication with the outside world is made synchronous again. Just the inside of the processor is asynchronous. This is relativly easy since you only have to make sure that the asynchronous path is travelled faster than a clock cycle.
The big advantage is that not every flipflop has to be active at every clock pulse and thus saves a lot of energy. Also the chip doesn't turn into a giant clock transmitter.

Jeroen

Re:Intel were first...

[h0tblack]

Read the story.. there were ARM based asynchronous chips in the lab (AMULET) a long time before 97.

way more elegant

[fizze]

the very first drafts of microprocessors were clockless.
just with higher speed and hence, brute force, performance could be achieved easily.
The problems which could not be solved back then were the obvious synchronisation issues. Setting up a common clock seemed the only way to resolve them.

The idea behind clockless designs is less a "back-to-the-roots" idea, but more a step to gain the advantages of such a design, which are, amongst others:

Reduced Power Consumption
Higher Operation Speed

Moreover, highly sophisticated compilers could tune program code to match a given performance/power ratio.

Yet, I would not bet on clockless cores to become the new mainstream, by far not. Clockless cores will most likely be aimed at embedded design appliances, and low- and ultra-low-power applications.

Re:way more elegant

[renoX]

Agreed that clockless cores have few chance to become mainstream, but still they have a better chance of being used now than before.

Let me explain: before to reduce power consumption the "easy" thing was to use a process which created smaller transistor, but smaller doesn't means 'reduced power consumption' anymore..
So clockless CPU becomes more interesting now.

Re:way more elegant

[Rattencremesuppe]

Yet, I would not bet on clockless cores to become the new mainstream, by far not. Clockless cores will most likely be aimed at embedded design appliances, and low- and ultra-low-power applications.

I think that "embedded appliances" are even more "mainstream" than anything else, since there are far more embedded systems around than general-purpose PC workstations, servers, laptops etc altogether.

Encouraging technology, but useful soon?

[Dancin_Santa]

The benefit to today's high-functionality embedded operating systems like Linux, Symbian, iTron, and Windows CE is that they implement a preemptive task switching operating system. At any time, the clock interrupt may fire and the operating system will then queue up the next thread into the CPU.

Nowadays, the whole CPU is not powered at any one time. If an instruction does not access certain parts of the chip, they are dark. Now this does not hold for some predictive processors which may be processing not-yet-accessed instructions, but in general if an instruction is not using some part of the chip, that part of the chip does not require juice.

Taking out the clock and relying on the chip parts to fire and return means that each application in the system must return to the OS at some point to allow the OS a chance to queue up the next thread. Without the clock interrupt, the OS is at the mercy of the program, back to the bad old days of cooperative multitasking.

The clock is what tells the OS that it is time to give a time slice to another thread. If we say "OK, well we'll just stick a clock in there to fire an interrupt every x microseconds," then what have we accomplished? We are back at square one with a CPU controlled by a clock. No gain.

This kind of system would work in a dedicated embedded system which did not require a complex multitasking operating system. Industrial solutions for factories, car parts, HVACs, and other things that need reliability but don't really do that much feature-wise seem to be prime candidates for this technology. "Smart" devices? Not so much.

Re:Encouraging technology, but useful soon?

[fizze]

Preemption is a "dirty hack" to achieve nice behaviour in a timely manner.
For embedded systems where interrupt latency is the primary aspect, other approaches have to be found. also, if the CPU checks after every x instructions if there is an interrupt to process, you get a margin of the timely behaviour.
I am no embedded / safety critical developer, but I know that the fastest response times on interrupts and worst-case response times vary greatly depending solely on the (RT)OS used.

Re:Encouraging technology, but useful soon?

[Anonymous Coward]

I think you are getting clock confused with ticker interrupt. A CPU clock is typically measured in nanoseconds. A ticker interrupt is typically measured in milliseconds. A clockless core will still need to field interrupts (for I/O) and very well can still field a ticker interrupt. -cdh

Re:Encouraging technology, but useful soon?

[CaptainAlbert]

You appear to be confusing the CPU's clock with a real-time clock interrupt. They are fundamentally not the same thing.

The clock being dispensed with is the one that causes the registers inside the CPU to latch the new values that have been computed for them. At 3GHz, this happens every 333ps. The reason this clock exists is basically because it makes everything in a digital system much, much easier to think about, design, simulate, manufacture, test and re-use. But, it's not an absolute requirement that it be present, if you're clever. (Too clever by half, in fact.)

The other clock, which you were referring to, fires off an interrupt with a period on the order of milliseconds, to facilitate time-slicing. If your application requires such a feature, you can have one, regardless of whether your CPU is synchronous or asynchronous internally. It's a completely separate issue.

Re:Encouraging technology, but useful soon?

[KiloByte]

We're talking about two different types of clocks:

• a timing source needed to preempt a long-running task
• the heart-beat that dictates when the CPU is going to do the next instruction.

These two are completely different things. The former can have a pretty low resolution as well -- but is needed for other tasks as well. Any non-degenerate processor will need some kind of timing source, but there is no reason why it would be connected to the number of instructions executed.

In a multitasking operating system, there are three reasons that can trigger a preemption:

• a hardware interrupt
  Some outside even has happened. A new bit/byte came in from a serial source, an IO tranfer ended, etc, etc.
• resource needed
  The process requires some resource that is either held by another process or will require an IO.
• the time-slice has expired
  A timer interrupt is needed for this, but nothing bad will happen if the resolution is many orders of magnitude bigger than the CPU core clock would be. You don't preempt processes every a handful of CPU cycles, do you?

Re:Intel were first...

[kf6auf]

So the question is WHY didn't it make it out of the lab? Did it cost too much to produce? That's the only real possibility I can think of - I don't think Intel's Marketing Division had absolute power over the company in 1997 to push the MHz agenda.

Quite impressive...

[Goalie_Ca]

The complexity of souch a core must be astounding. For all you non-ee's out there, a chip is full of little memory cells called flip-flops. At the end of each circuit rests a flip-flop in which normally the rising edge of the clock stores the results of that circuit so it pass that data on and start new stuff without loosing it. Everythig is synchronized to the clock. This is definently over-simplified but that's essentially why a circuit has a clock.

To eliminate clocks you would new circuitry such arbitrers and some sort of completion logic which could be used to trigger a flip-flop. To break a slashdot law, i haven't done any reading on any modern techniques so would some one enlighten me on some design issues involving simple tasks such as accessing a register file, or making a memory read. Surely a bus would still maintain a clock.

Re:Quite impressive...

[rahard]

To eliminate clocks you would new circuitry such arbitrers and some sort of completion logic which could be used to trigger a flip-flop.... enlighten me on some design issues involving simple tasks such as accessing a register file, or making a memory read.

if you remember your digital design, there's an asynchronous counter. basically, it involves handshaking just like handshaking in a protocol level but at a lower level. yes, there's arbiter, muller c-element (rendezvous), and other nifty components.

the most novel approach, IMHO, would be ivan sutherland's micropipeline which could be extended into Counterflow Pipeline Processor (CfPP). Here is his Turing Award paper on micropipelines. (very good and readable paper!)

Other keywords include "self-timed". I believe there's somebody @ SFU Computer Science who did asynchronous design. I forgot the name. (sigh)

Re:Quite impressive...

[drmerope]

Since you expressed a particular interest in register files, here is a recent publication:

David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, April 2004.
http://vlsi.cornell.edu/~rajit/ps/reg.pdf

The fastest/lowest energy asynchronous circuits do not use clocks for anything. Moreover, very few arbiters are used in practice. The "completion logic" of course is always the hard part, but about 10 years ago, something called "pipelined completion was developed" which alleviates that bottleneck.

For how arbiters are used and avoided:
Precise Exceptions and Interrupts in Asynchronous Processors. Rajit Manohar, Mika Nystrröm, and Alain J. Martin. Proc. 21th Conference on Advanced Research in VLSI, IEEE Computer Society Press, March 2001.
Crossing the Synchronous-Asynchronous Divide. Mika Nyström and Alain J. Martin. Workshop on Complexity-Effective Design, 2002

Re:Intel were first...

[jimicus]

No they weren't. From TFA:

The AMULET1 microprocessor is the first large scale asynchronous circuit produced by the APT group. It is an implementation of the ARM processor architecture using the Micropipeline design style. Work was begun at the end of 1990 and the design despatched for fabrication in February 1993. The primary intent was to demonstrate that an asynchronous microprocessor can offer a reduction in electrical power consumption over a synchronous design in the same role.

Not relevent

[r6144]

As far as I know, Linux and many other operation systems already use an external chip (the 8254 on the PC) for most timing tasks, including preemptive multitasking. For ultra-high precision timing, the CPU clock (the time stamp counter on an IA32 cpu) is used, but they are not all that essential. Last time I heard, since CPU frequencies can change by power management functions on some P4s, they are a bit tricky to use correctly for timing, so they are not used when not absolutely needed.

As for the power problem, all parts of the CPU is powered, except that gates that aren't switching consume less power (mostly leakage, which seems to be quite significant now). In synchronous circuits, at least the gates connected directly to the clock signal switch all the time, while in asynchronous circuits unused parts of the CPU can avoid switching altogether, so some power may be saved, but I don't know how much it will be.

Re:Not relevent

[Scarblac]

You didn't understand what this is about. It's not about timing.

You talk about "CPU frequencies". What is that? That's the frequency of the CPU clock signal. It runs everything inside the CPU - at every 'tick' of the clock, instructions move through the CPU, registers are updated, etc. This is about CPUs that don't use a clock signal at all, different things happening aren't synchronous. These CPUs don't have a frequency.

(Probably wrong also, I don't have the time to express myself more clearly - just wanted to point out that what chip to use to keep track of time is completely besides the point)

ARM Business Model

[joelethan]

I'm interested becasuse ARM's business model usually involves licensing their chip designs. ARM cpus are widespread in cell phones etc. They have their own market and application area away from Wintel, PowerPC etc.

Also, anything that might boost my pitiful ARM shares value is most welcome! Why?... Why did I believe the hype?

/joelethan

ENIAC was first

[chris_sawtell]

I hope they don't try to patent this.
Refer to 1944 for prior art.

Re:Intel WAS first

[Anonymous Coward]

Ummm considering that British English is the Original English, I think those speakers can make that "mistake" as many fucking times as they want. Now STFU and go choke on a freedom fry, you (obviously) American prick.

standardised implemenation.

[Anonymous Coward]

When I was at university we studied standard ways to overcome these problems down to gate and transistor level. The impression i was given that its not that hard. Some of the standard ways include doing a calculation twice and waiting for the results to be the same. Of coarse there are no tools to do it in automated fashion that i am aware of like synchronous design. Here the tools are extensive from vhdl to handel C implenentation. Even dynamic logic can be synthesised automatically now. This means its to risky for asic design houses to implement on there own as they would have to do there own custom blocks. This also presents a design flow problem. How would a foundry verify the design for you. In the case of synchronous design the methodology is well established.

my 2 cents..

Idea has been around for 30 years

[gtoomey]

These asyncronous computers are implementations of data flow computers.
The problem is that the first implementations were very slow.

Re:Philips growing into a Major R&D company

[dtmos]

Philips has been a world-class R&D company for a long time. Philips Research was established in 1914, and has contributed much, from the invention of the pentode vacuum tube (valve) by Tellegen in 1929 to the audio cassette in the 1960s and their more modern work developing CDs and DVDs.

The fire has been lit under IBM and other corporate research organizations for a long time.

I had an idea once

[ajs318]

The reason why a clock is commonly used in microprocessor circuits is to try to synchronise everything, because different logic elements take a different amount of time for the outputs to reach a stable state after the inputs change. This is known as "propagation delay" and is what ultimately limits the speed of a processor. With CMOS, you can actually reduce the propagation delay a little by increasing the supply voltage, but then your processor will be dissipating more power. {CMOS logic gates dissipate the most power when they are actually changing state, and almost no power at all while stable, whether they are sitting at 1 or 0. This is in contrast to TTL, which usually dissipates more power in a 0 state than in a 1 state, but there are some oddball devices that are the other way around}.

The clock is run at a speed that allows for the slowest propagation, with data being transferred in or out of the processor only on the rising or falling edges. This allows time for everything to get stable. It's also horrendously inefficient because propagation delays are actually variable, not fixed.

If you wire an odd number of NOT gates in series, you end up with an oscillator whose period is twice the sum of the propagation delays of all the gates. If you replace one of the NOT gates with a NAND or NOR gate, then you can stop or start the oscillator at will. Furthermore, by extra-cunning use of NAND/NOR and EOR gates, you can lengthen or shorten the delay in steps of a few gates. Obviously at least one of the gates should have a Schmitt trigger input to keep the edges nice and sharp; but that's just details.

My idea was to scatter a bunch of NOT gates throughout the core of a processor, so as to get a propagation delay through the chain that is just longer than the slowest bit of logic. Any thermal effects that slow down or speed up the propagation will affect these gates as much as the processing logic. Now you use these NOT gates as the clock oscillator. If you want to try being clever, you could even include the ability to shorten the delay if you were not using certain "slow" sections such as the adder. This information would be available on an instruction-by-instruction basis, from the order field of the instruction word. The net result of all this fancy gatey trickery is that if the processor slows down, the clock slows down with it. It never gets too fast for the rest of the processor to keep up with. Most I/O operations can be buffered, using latches as a sort of electronic Oldham coupling; one end presents the data as it comes, the other takes it when it's ready to deal with it, and as long as the misalignment is not too great, it will work. For seriously time-critical I/O operations that can't be buffered, you can just stop the clock momentarily.

The longer I think about this, the deeper I regret abandoning it.

Re:I had an idea once

[ajs318]

That's another reason to scatter the delaying gates throughout the core, and use enough of them. You have to hope that you don't get too many instances of a logic element and one of its associated delaying gates falling on the opposite sides of a process variation boundary. Especially where the effects favour faster propagation in the delaying gate. So, my intention was to aim for the clock delay being slightly but definitely longer than, and not exactly equal to, the logic delay. It would still respond to dynamic effects like temperature better than an external clock oscillator.

This would also be one of those kinds of circuits that, if it's not built on the same silicon substrate, won't work at all. Power op-amps are another good example: they rely on better thermal coupling than you can achieve with discrete components, and better properties-matching than you can achieve by just pulling transistors out of a bag at random without doing any tests on them. {You can't control the absolute values of most on-chip components precisely, but you can be fairly sure of the relative similarities between them}. Build one out of carefully-gain-matched transistors exactly according to the schematic in the data book, and it might just about work if you put it in a constant-temperature oven. In the best case it will distort like hell, and in the worst case it will go literally into meltdown.

Re:I had an idea once

[chrysrobyn]

My idea was to scatter a bunch of NOT gates throughout the core of a processor, so as to get a propagation delay through the chain that is just longer than the slowest bit of logic.

I assume that you hope to use your self timed logic (as it's known in the industry) to avoid all the problems associated with clocked logic and provide an easy to use asynchronous solution. Please do not forget manufacturing tolerances and that you have to make your self-timed logic 99.99999% certain slower than the slowest asynchronous path. This means that you have to qualify your entire logic library with a specific technology, then guardband it to make sure that when manufacturing shifts due to reasons you cannot explain, your chip still works. For this reason, in my experience, self timed logic has been slower than clocked logic for nominal cases and much slower in fast cases (in special cases, better than breaking even in slow process conditions).

Self-timed logic of the kind you describe would likely still end up with latches to capture the result / launch into the next self-timed logic block. In this case, you're still paying the latch cycle time penalty for clocking your pipeline. You're still burning the power associated with the clock tree (although you are gating your clocks to only the active logic, known as "clock gating", an accepted practice), and you're additionally burning the power for each oscillator, which I suggest would likely be more than the local clock buffers in a traditional centrally PLL clocked chip.

An ideal asynchronous chip would be able to not use latches to launch / capture and still be able to keep multiple instructions in flight -- using race conditions for good and not evil. This would involve a great deal of work beyond simply using inverters and schmitt triggers. This is a larger architecture question requiring a team of PhDs and people with equivalent professional experience.

Re:I had an idea once

[TonyJohn]

You stated that the clock period (and therefore the length of the ring oscillator) should be about the same length as the critical path through the design. This is likely to be significantly less than 50 gates, and therefore your oscillator will only have 25 inverters. In a design with a million gates or more, this is not really enough to monitor the process and temperature variation across the die (which is surprisingly significant). If you could get enough gates into the ring (use NAND gates?), then they will start consuming significant area, and therefore slow the chip down.

The idea is good and the physics is sound, but putting something like this into practice is much harder than you make out. Speed binning of chips goes part way to adjusting for process variation. Sophisticated chips have temperature monitors that will scale back the clock when things get too hot (but in a crude, broad-brush way). ARM is already working on more fine-grained closed-loop systems (see here), but as a way of saving power rather than going faster, and with an indirect link between chip speed and clock.

Way Back When

[opos]

A long long time ago (1970s) Charlie Molnar, designer of the Linc tape (the Linc computer was an NIH funded (late 1960s) minicomputer that evolved into the PDP 8 and pushed DEC into the minicompuer business) explored asynchronous computing. Along the way they discovered synchronizer failure - i.e. the inability to reliably synchronize asyncronous subsystems - see Chaney, T.J. and Molnar, C.E. 1973. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comp. pages 421-422. The bottom line is that it is physically impossible to guarantee that the data setup requirements (the minimum time the data must be asserted before it can be reliably clocked into the flip flop) of a flip flop can be met when the clock is asserted by one async component and the data are asserted by another async component. To my knowledge, this fundamental limitation has never been overcome.

Re:Way Back When

[BarryNorton]

A good review, as well as the state of the art, afaik, in showing how much we can formally say about what can be achieved practically is Ian Mitchell's MSc thesis (1996, British Columbia) 'Proving Newtonian Arbiters Correct, Almost Surely' (which is an answer to Mendler and Stroup's 'Newtonian Arbiters Cannot Be Proven Correct', paper versions of both being available from the proceedings of Designing Correct Circuits, in 1992 and 1996)

Interesting...

[dkf]

It looks like Philips (through their tame spin-off Handshake Solutions) are letting the world see Tangram again (or something very like it.) Back in around 1994/1995 the Amulet team (already mentioned accurately by others) were looking into using the Tangram language to develop their asynchronous microprocessor technology - it was a fairly neat solution that did most of the things we wanted, though there were a few things it was crap at at the time - but then Philips decided to cut us off. It would be entirely fair to say that this was very annoying! Now it looks like they're letting the cat get its whiskers out of the bag again.

FWIW, ARM have probably known (at least informally and at a level not much deeper than your average slashdot article) a large fraction of what Philips have been up to in this area for at least a decade.

The WIZ Processor

[MarcoPon]

Take a look at The WIZ Processor, by Steve Bush.
It's a drastic departure from common CPUs. Definitely intresting.

Bye!

Re:The WIZ Processor

[MarcoPon]

Also this thread on MASM forum could be of interest. It was started by Steve Bush himself, and there are a lot of discussions & examples from the point of view of the ASM programmer (but not only that):
The WIZ - a new and radical processor architecture

P.S. I'm not associated with Mr. Bush in any way; I simply like this kind of things.

Bye!

The 68000 had async operation with /dtack pin

[Anonymous Coward]

This was the purpose of the /dtack pin. This was used to acknowledge a transfer when operating async, or you could just ground it and run things at cpu self clocking sync. So how is this new again?

Re:The 68000 had async operation with /dtack pin

[vidarh]

Because that was for async bus operation, not async internal operation. The 68000 is fully synchroneous internally, as most/all other commercially successfull CPU's. Async buses is nothing new, and the ability to support it on the 68000 was in fact mostly to allow it to integrate with older hardware.

Sun has also done work in this area

[mdxi]

In 2001 they presented a paper on an asynch processor design called FLEETzero/FastSHIP. According to the patents list on this page, they're still doing work on it (see also here.)

Re:Intel were first...

[Anonymous Coward]

The biggest problem with asynchronous chips lies in the fact that all the design tools, fabrication facilities, and testing methodologies are geared toward synchronous processors. If Intel or any chip maker were to release an asynchronous processor on a large scale, it would require a MASSIVE overhaul of the industry. It's an investment that requires both time and money on a risky departure from decades of acquired knowledge in designing synchronous chips.

NO NO NO!!!

[kompiluj]

Give me back my gigahertz!!!
I want all my precioussss... gigahertz!!!