RIP Pentium II, 1997 - 2006
zorn writes "The Register has the scoop that 'this week Intel told its customers that it is to formally discontinue production of the Pentium II at 266, 333, 366 and 466MHz. Documentation seen by The Register reveals that you'll be able to continue ordering the part for a year, with the last trays leaving the chip giant's Pentium II warehouse on 1 June 2006.'"
I don't know how they can claim it's discontinued if it never existed in the first place...
the P2 switched to 100Mhz FSB at 350Mhz, thus a P2 366 and 466 never existed. Since those are for embedded, they might be talking about mobile P2 - 366 mobile P2 indeed exists, but a mobile P2 466 does not (fastest P2 ever was 450Mhz, fastest mobile 400 Mhz).
And btw, the register gets it wrong: that it is available so long has nothing to do with power consumption and the like, it's simply because certain industry applications require that a chip is available for a long time - embedded chips are still in use after 20 years or so, and it's good if you can still get replacement parts.
We use Pentium 2s on some of our embedded systems, but by the time 2006 rolls around we'll be done using them.
Our newer embedded systems use Pentium 3s.
Actually, some of our basic systems (that we ship on a regular basis) still use plain old Pentiums running @ 200MHz. The processor is basically permanently attached to the board it comes on. It's amazing how small of heatsink it requires.
I've got PIX firewalls built around socket 370 Celeron variants of the Pentium II. The slowest of these PIX firewalls can handle 100 times the amount of internet traffic we could ever think about affording.
Recently Cisco moved to a 133 MHz AMD cpu in their PIX 501. Their higher end PIXes use Socket 370 Celeron and Pentium III chips.
-ted
The McDonald's Arch Deluxe: a product before its time.
Try here to make your own.
PPro (6th-generation, OOOE, Register renaming, fully pipelined ALUs/FPU, etc. .5 micron, 120-200 MHz) ->
.35 micron shrink, 233-300MHz) ->
PII Klamath (Added MMX, better 16-bit performance, external cache,
PII Deschutes (.25 micron process shrink, added official 100MHz FSB, basis for Celerons, 300-450MHz) ->
PIII Katmai (.25 micron optimization, added SSE, introduced official 133MHz FSB 450-650MHz) ->
PIII Coppermine (.18 micron shrink, added on-die 256K cache on 256-bit bus, 500-1133 MHz) ->
PIII Tualatin (.13 micron shrink, bumped cache to 512K, used new incompatible bus protocol, 600-1400 MHz)
Man is the animal that laughs.
And occasionally whores for Karma.