Intel Expands Core Concept for Chips

Aziabel writes "As most of you have probably heard, Intel plans to come out with chips containing two processing cores next year, but that's just the start. The Santa Clara, Calif.-based chip giant intends to exploit the concept of using multiple processor cores; chips with four cores and eight cores will eventually join dual-core chips, which will begin to appear from Intel next year. The company's research department is also looking at the feasibility of creating chips with hundreds of cores to assist servers and supercomputers with large numbers of relatively repetitive calculations, said Steve Smith, vice president of the desktop platforms group at Intel. The focus on multiple cores arises from Moore's Law, which dictates that the number of transistors on a chip doubles every two years. I say, the more the better. Keep 'em coming, chip-makers!"

Comments

Performance rateing

[Barny]

The problem is with what they (both intel and amd) plan to do is saying a dual core 1.5 centrino (for example) cpu is actually a 3Ghz machine (from the pr they have allready put out about these chips).

Read overclockers.com for some good speculation on what the good/bad/ugly features are likely to be.

Re:hmm

[jackb_guppy]

A core ~= A processor today. So multi-processor OS is nothing new. Shoot Intel Hyper-Threading is not new - It looks to OS as two processors but only 1 is running at given time.

You see an OS runs multiple threads in the first place it just switches between them as each need run time.

But for given program to be written to use 2 or more threads (looks to the OS as 2 or more programs) takes work.

So take a program that is already written and place in a multi-core/processor/thread enviroment with all else being equal - it will run as fast as it did before.

What will run faster is all of it. Take two of these old programs and run them in the multi-core/processor/thread enviroment and they each take same processing time unto themself, but the obversied time is shorter because they are both actually running at SAME time.

Re:OOH object oriented hardware

[Anonymous Coward]

For what it's worth, this is very close to the basic ASIC architecture used in IBM's BlueGene/L. Each board has two chips with separate memories. One chip is always slaved into being the I/O manager for the other chip. Boards are arranged in rack mounts, which are arranged in enclosures, with a grid of enclosures being the entire supercomputer. One board for each rack handles the I/O for the rack (with its slaved chip still handling its own I/O). One rack for each enclosure has its processing chips handling I/O for the enclosure (with its slaved board handling its own I/O).

Because all of the chips are identical, they can dynamically reassign tasks as chips, boards, racks, etc. fail. The I/O chips spend their cycles distributing processes and data across all of the processing chips and their memories.

Sun already ships this

[eclectus]

Sun's new Ultrasparc IV shipped in the SunFire 490's and larger servers already do this. The plans right now are to scale this up to 32 cores per cpu. The only issue that I see is that the memory controller is onboard the cpu, so while you may have 2/4/8/16/32 cores, you still only have a single memory controller, which limits the ammount of ram you can have. I'm sure they have a solution for this, but I don't know what it is.

Yes they do

[Groo Wanderer]

Yeah, it is called Niagara, and it is working silicon now, but far from done. expect an unveiling in February.

If you want to know a bit more about it, I wrote it up a few weeks ago here:
http://www.theinquirer.net/?article=19423

-Charlie

Intel is not doing all that well in the core races

[Groo Wanderer]

Intel just canned their 8-way chip and replaced it with a variant of Montecito, or more likely a Montvale derivative. Here is a bit on it:
http://www.theinquirer.net/?article=20270
ht tp://www.theinquirer.net/?article=20286
Needless to say, their long term strategies are a tad up in the air right now.

As for their desktop (IE P4 based) dual core plans, there are 2 generations planned. The first is a simple pairing of 2 current cores with a minimum of tweaks, basically a scared response to AMD. The second one is really the first one they planned, and it is a lot more sophisticated.

AMD was there from long before Day One, and have the most coherent philosophy on dual cores for the desktop/server.

Rather than re-write all my own articles here, here is a link where I break down all of Intel's dual core plans as well as some of AMDs.
http://www.theinquirer.net/?article=17906

Sorry for all the self links, but I don't really want to keep re-writing that stuff, links are the reason behind the web, right? :)

-Charlie

Re:Dual cores for Intel next year?

[phoenix_rizzen]

Cache coherance, cache access, and bus contention are only problems for Intel. AMD solved most of these with the Athlon-MP and HyperTransport, and solved the reset with the Opteron's integrated memory controller.

In AMD SMP systems, each CPU has its own separate link to RAM and peripherals. Each CPU also has a link to each other CPU. If CPU A needs something in CPU B's cache, it just asks CPU A to send it that data across the inter-CPU link.

As you add CPUs in an Opteron server, you actually increase the RAM/system bandwidth. Compare that to a Xeon system where adding CPUs reduces the bandwidth available to each CPU (system/RAM bandwidth is constant).

There's a beautiful set of articles over at Ars Technica describing the SMP abilities of the Athoon, the Opteron, and the Xeon. It's amazing Intel has been able to sell any 8-way systems.

Rumor: another Intel catch-up move

[museumpeace]

I was going to post this anonymously because the person who told me about it works at Intel and needs no more grief. But ths morning, I was able to find confirmation from VNUNET and /. editors are unlikely to put up two Intel chip stories in one day so I am not submitting a story. Why make it so NOBODY ever hears this news?
Intel is, no make that was, rumored to be, [no, definitely are] in the process of buying the design group that develops Itanium from HP.
The vnunet page has a little speculation as to why the move is being made. But if you put that together with HP's general strategy of streamlining its fragmented high performance server offerings:

Martin Riley, HP's Alphaserver business manager, admitted the migration would take some time. "HP has staked its future on its servers being architected around Itanium, whether they are HP-UX or OpenVMS. Itanium has a 20-year lifespan. Customers will not move immediately [to Itanium], and most are planning their transitions in 2006."

Then the picture that emerges is in agreement with parent comment: Intel is in catch-up mode. They have, as other stories and commenters have pointed out in /., ceded a few points to AMD in the 64bit architecture wars and are doubtless uncomfortable not holding a microsoftish position of utter dominance.

Re:Cell Processor

[wik]

This increases the fabrication costs for the silicon die because the processes used to create high-performance CMOS logic and high-density DRAM are different. Because of the cost, it's not likely to happen for commodity microprocessors any time soon.

Re:Not that kind of law!

[danila]

Most desktop applications can use parallel processing just fine. Word processors, music players, image editors, etc. all can break the job into small independent chunks. But as much as I would appreciate faster processors, I'd enjoy faster storage devices even more. Even though my CPU is at most 10-15% active and only 40-50% of RAM is used, when enough applications want to access the disk simultaneously, the computer can slow to a crawl. I want better caching, more intelligent disk access prioritisation, faster HDDs or just solid state drives.