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Intel Expands Core Concept for Chips
Aziabel writes "As most of you have probably heard, Intel plans to come out with chips containing two processing cores next year, but that's just the start. The Santa Clara, Calif.-based chip giant intends to exploit the concept of using multiple processor cores; chips with four cores and eight cores will eventually join dual-core chips, which will begin to appear from Intel next year. The company's research department is also looking at the feasibility of creating chips with hundreds of cores to assist servers and supercomputers with large numbers of relatively repetitive calculations, said Steve Smith, vice president of the desktop platforms group at Intel. The focus on multiple cores arises from Moore's Law, which dictates that the number of transistors on a chip doubles every two years. I say, the more the better. Keep 'em coming, chip-makers!"
It's nothing more than a catch-up move to Sony/Toshiba/IBM Cell, just like EMT64 to catch up AMD. Those late and awkward moves are of bad omen for Intel, IMO.
"The focus on multiple cores arises from Moore's Law, which dictates that the number of transistors on a chip doubles every two years. I say, the more the better. Keep 'em coming, chip-makers!"
No. I think it arises from the limits of the von neuman architecture.
This does not bode well for problems that mathmatically cannot be executed in parallel.
if a kernel is written to take advantage of multiple cores, would this mean applications written ontop of it would start using the multiple cores?
if not, how feasable is a multicore > single core emulation in linux.
Gordon Moore, the guy the "law" was named after, works for Intel. Intel puts a fair bit of weight behind the notion behind it, and they even have a page on their research section about it.
Most of the reports that I have read have said that AMD will be releasing theirs next year and Intel the following year. Intel, though didn't start talking of dual cores until AMD started talking about theirs. From research that I have done, each manufactorer has some mighty issues to overcome with the single core before dual cores can be implemented nicely.
AMD has said that dual cores will be clocked anywhere from 600Mhz to 1Ghz slower than the single core counterpart, namely because of heat issues. There are many more issues that arise with dual cores here are a few
Cache correnance
Bus contention
software implementation
plus more
It will be interesting none the less on how each manufactorer overcomes the issues with multi-core chips and the benefits to the user of of multi-core.
A few years ago I thought of a different kind of twist on computer architecture that I labelled OOH.
The basic idea is that a computer could comprise many, many tiny CPUs, each with its own tiny local memory.
A given (CPU+RAM) could be designated to operate as RAM for another CPU, so the MMU/OS could balance the number of processes needing memory with those needing processors.
A (CPU+RAM) could also be labeled as a slave to others, so a multithreaded application could have the number of processors it needed.
I haven't thought about it in a while, and it's been some time since I studied architecture, so probably these ideas are hopelessly naive.
Raise your children as if you were teaching them to raise your grandchildren, because you are.
"Laws" like Moore's, Newton's, Ohm's and others, don't "dictate" anything. They "describe" observations. Intel doesn't meet integration targets based on some hoary old directive from Gordon Moore from the late 1960s. They meet production deadlines projected as close to their maximum productivity. Moore observed the logarithmic rate of transistor integration increase way back then, and described it as invariable as gravity.
Engineers especially must understand that "laws" of nature, including human innovation, are governed by an "invisible hand". Not some imaginary deity, or some government, or some mythic genius. Rather, there is a deeper order to events, like the way every triangle has 180 degrees, the Sun "comes up" every morning, controversial Slashdot posts will get mod'ded "Troll", without any false statements or duplicity. We're engineers: our job is to engage the deeper order, understand it, model it, and exploit it, without further mystifying it.
--
make install -not war
This is much less of a problem than you might thin, not because it isn't a real problem, but because it is so obvious. Everyone already has a workaround, most of which involve FB-DIMMs.
Niagara (see my post above) is bandwidth rich, the AMD solutions are also. The only ones with a looming problem are Intel until CSI comes on in a few years, but that is manageable.
Moral, Sun OK, AMD OK, Intel solid plan.
-Charlie
Excuse me but IIRC Tera is more a multi-threaded processor, not a multi-core. It was intended to run 128 threads simultaneously, and solve the memory latency problem by running each thread in succession. The idea was that if a thread was stalled by a need to access main memory, by the time it got back around to that thread again the data would have arrived. Overall throughput was supposed to put it into the supercompuer class.
You're right that the processor didn't succeed, probably because in practice it didn't preform as well as the theory sounded. What I never understood was that given all the problems in the first Tera machine, why the UCSD-SCC then went back to them and spent to much additional money on a second one?
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."