Slashdot Mirror


More Cell Processor Details And First Pictures

slashflood writes "After reading two articles on slashdot about the Cell architecture and another one that criticizes the extensive roundup of the STI patents, I found the first pictures of the Cell core. It seems that at least some predictions were true. Seeing is believing." mtgarden points to this ZDNet article which says that the "first version of the chip will run at speeds faster than 4GHz. Engineers were vague on how much faster, but reports from design partners say 4.6GHz is likely. By comparison, the fastest current Pentium PC processor tops out at 3.8GHz." (More below.)

Hack Jandy writes "Anand Shimpi has some details about the upcoming Cell processor (PS3) in his personal blog. According to Anand, "Rambus announced that the new Cell processor uses both Rambus XDR memory and their FlexIO processor bus. Because Rambus designed the interface for both the memory controller(s) and the processor interface, the vast majority of signaling pins are using Rambus interfaces - a total of 90% according to Rambus." Hasn't Rambus been showing up a lot again recently? The fact that Cell uses XDR has been widely speculated, but the fact that it will also use the Rambus bus signalling is something completely new."

13 of 535 comments (clear)

  1. Cell by ryanmfw · · Score: 5, Interesting

    Cell processors could really dominate. With how cheap they arespeculated to be, their distributed processing, and their all around speed, the could take over a significant part of the computer marketshare. If Cell processors also have the Power4 processors in them, this could be a replacement for x86. Could be. As other articles have pointed out, x86 has had superior competition in the past, and has been able to weather it. We shall wait and see. Cheers

    --
    Hurricane Ivan: A 17th century prison collapsed. All of the inmates escaped.
    1. Re:Cell by hattig · · Score: 5, Interesting
      From http://www.aceshardware.com/forums/read_post.jsp?i d=115121622&forumid=1

      CELL is a Multi-Core Architecture
      Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
      Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design - views system memory as a 10-way coherent threaded machine
      2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
      234 million transistors
      Prototype die size of 221mm2
      Fabricated with 90nanometer (nm) SOI process technology


      We're talking about a single-core POWER5 design (because of the SMT).

      But 221mm^2 ... that's big, bigger than a 130nm Opteron, bigger than a dual-core 90nm Opteron. But wait for 65nm, and you've got something of a manageable size to make a cheaper console. I don't see 4 Cells in a PS3 though, not even at 65nm, unless it is going to cost a boatload. Still, Sony aren't a little company, I'm sure they could sort it out.

      Still, I guess this means the next PowerMac G5 will be using processors with SMT finally.
  2. PS3 by clean_stoner · · Score: 4, Interesting

    The Cell is going to be in the PS3, so does that mean that the PS3 will be clocked at 4.6 GHz+? That seems like a big leap considering consoles are normally running a little slower than "good" computers at the time they come out.

    --

    Sigs are for the weak.

  3. We flame Intel for touting speed... by X43B · · Score: 5, Interesting

    I'm waiting to see how much work it can actually do before making a judgement. At the least it always exciting to have another option. I wonder how difficult it will be to take advantage of the new architecture.

  4. Re:Xbox by Thu25245 · · Score: 5, Interesting

    Thing is, the next Xbox will be using a PowerPC 970. So it will share a common ancestor (POWER) with the Cell.

    I wonder, how compatible are the two CPUs' instruction sets? Will Microsoft be able to drop a Cell into a future revision of the Xbox2 and maintain backward compatibility? Could someone theoretically hack a PlayStation3 to run Xbox2 games?

  5. Re:Speed isn't everything by MBCook · · Score: 4, Interesting
    That's true. But there are two important things here. The first is that it's at 4ghz. The P4 hasn't been able to reach that (though Intel origionally said it would happen by now). So it's all ready up there.

    The second is that it's STARTING at 4ghz. It's one thing to say a chip can scale and run at some speed (again, I'm looking at you Intel), but to debut it running faster than the fastest mass produced CPU in the world is something all together different.

    Cell should be quite formidable, and I think it will be quite interesting to see what comes of it. I've held the opinion for a few years that computers would move to having a couple of CPUs each running their own task (like in Cell), with one main (quite possibly slower) CPU controlling them all and running the OS (traffic cop, again like in the Cell). While the individual processing units are not general purpose (they are more vector oriented), it should still be interesting to see what comes of this. After all, most things people use high-end CPUs for are (or can be) vector ops, right? Compression, 3D, etc. Wordprocessing and spreadsheets don't tend to need much power. A large generalization, I know, but still... the introduction of the Cell (especiall the way it should be able to "group" its self with other Cell processors in your house) should prove quite interesting even if it turned out to be a failure (which I SERIOUSLY doubt.)

    --
    Comment forecast: Bits of genius surrounded by a sea of mediocrity.
  6. Conspiracy Theory by Sophrosyne · · Score: 3, Interesting

    fact #1 Apple and Sony have been awfully close for the past few years- with some dialogue between the two CEOs.
    fact #2 Apple has signed up to display at E3 this year- but hasn't published any official info on their site.
    fact #3 The Mac is somewhat deficient when it comes to gaming when compared to the Windows PC.
    So my speculation is that it is possible that Apple intends to build a new Mac aimed at the gaming market that will be compatible and play Sony's PS3 games- Apple in turn could publish games for the PS3.

  7. Apple's connection to the Cell processor by bonch · · Score: 3, Interesting
  8. Power consumption by Anonymous Coward · · Score: 5, Interesting

    For those of you wondering about the power consumption of this thing, perhaps you should note that Sony just licensed LongRun2 from Transmeta. It is a dynamic solution for power consumption and leakage that will probably end up in the 65nm versions coming out next year. google transmeta sony for more.

    Once touted as the Intel killer, perhaps Transmeta will finally have its day.

  9. Re:Speed isn't everything by Johnno74 · · Score: 3, Interesting

    As the grandparent post said, MHZ != performance.
    A good analogy tell computer illiterate people is MHZ is kinda like the RPM an engine will do. Higher RPM doesn't necessarily mean higher speed.

    Also, its a RISC design. it may well do LESS in each clock cycle than x86.

    And aren't we close to the theoretical limit transistors can switch at? If the cell processor starts at such a high clock rate it won't have as much headroom for improvement.

  10. I did, I'm still confused by mcc · · Score: 3, Interesting
    Hi.. so I am trying to take all of this in. Please help me understand. I am a Mac programmer and I have a relatively good understanding of what's happening in the PowerPC. I'm a bit confused about some elements of this Cell thingy though.
    • So the CPU is just a normal POWER, right?
    • But, from the article: "Along side these is a 64-bit Power processor capable of running two threads." "Capable of running two threads"? Is this the same as hyperthreading in the intel processor? I did not know IBM was working on their own implementation of that, have multithreading POWER CPUs been used in a product yet?
    • It says t*he vector unit is a "VMX", well, that's just the same thing as Velocity Engine / Altivec that Apple uses, it's just a different brandname, right? And that'll be just part of the POWER, like the Altivec unit would be on a PPC?
    • The SPEs/APUs/"stream processors" are in particular what's confusing me just a little. I can think of lots of circumstances for which these things would be useful. But what I don't get is why, if you have these things, you still need the VMX. For what purposes is the VMX more suited? Has it got better throughput for the applications to which it is suited? Does it work better with the main CPU than the SPEs? Or is the idea here just that you don't have to keep the SPEs busy doing stuff that a normal VMX could handle?
    • Here's my big concern: on the Mac, the big problem with altivec has been keeping the altivec units fed. A lot of the time the altivec isn't getting used for anything, and even when it is, prior to the G5 there were serious problems with pushing enough data through the bus to keep the Altivec constantly busy. Will the SPEs have this same starvation problem? From the article: Connecting up the processing units is the element interconnect bus (EIB), comprising four 128-bit rings and a 64-bit tag running at half the processor clock. The busses connect to the SPEs through local memory, 256kbyte for each SPE. .. What is this telling us? That each of the SPEs has 256k of private memory to work with? Can SPEs freely read other SPEs "local memory", or only their own? And who fills up this memory initially, and who deals with it once it's done? The main processor? I.E., do the SPEs have access to main or video memory or other hardware, or do they ever require for the CPU to shuttle data to keep them fed? It appears from the original patent overview that the SPEs can talk directly to the memory controller, so if I'm reading that right then that's good-- that seems to make them qualify as actual processing units and not just coprocessors like the VMX is. But then the article seems to be saying the is SPE access to memory is limited-- i.e. it can only be done in block load/stores. Well, are there other limitations, can the APUs talk to (for example) video memory?
    • But, crucially, who loads the instructions for all of this?? If we've got a CPU that can be running two threads, and 8 little APU/SPEs that are each effectively running as their own processor, and all of this is sharing one memory bus... that's like effectively ten instruction streams to be reading at the same time. Is that going to be a problem? Do each of the 8 SPEs actually independently load their own instruction streams? Or is the idea that they partially use that 256k "local memory" as effectively an instruction cache?

    If you can help clarify some of this for me, thanks.
  11. They already tried this on PS2! by jbischof · · Score: 3, Interesting
  12. context switching by ArbitraryConstant · · Score: 3, Interesting

    As I understand it, the APUs can act semi-independantly but the controlling processor has overall control. If that's true, if the processor wanted to (say) switch to some other process would it have to save all that state to somewhere else before continuing, just as standard processors do now?

    As all the APUs have lots of big registers and significant amounts of private memory, wouldn't that be painful?

    --
    I rarely criticize things I don't care about.