Slashdot Mirror
Researchers Create 3-Dimensional Chips
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
It all depends on density of the transistors. You can squeeze 1 square mile into a 1 inch cube, but it will take 334,540,800 individual layers to do so.
Well, thye haven't been doing it ALL along, but they've been doing it more more than a couple years already.
P4's currently run on a 7 layer design and AMD 64's run between 4 and 9 layers depending on the specific model.
I'm sure IBM does the same also.
The key difference between a Programmer and a Senior Programmer is that one of them is Mexican.
This is really cool stuff. Essentially they're making silicon wafers smaller by removing all the silicon in the substrate after the wafer is fabbed. Then they can put this few-micron-thick layer onto another fabbed wafer - perhaps made with a different process - then they can repeat the process. This allows sensor, analog, processor and memory to be made in the best processes for each function but with communication channels tens of thousands of wires wide and only microns long.
This article is worth reading - this is going to be huge. Also there is a really fantastic picture of a see-through microprocessor wafer with the article.
From the article:
Wafer-level stacking also allows for short connections between different types of chips. "Particularly today the industry is trying to combine memory with the processor, and more than half of the chip is taken up by memory," Lu explains. "When we stack layers, we have a processor on the bottom and layer the memory on top, with a short access time between them." Lu says the reduction of memory access time would be a huge advancement for large-scale computer clusters calculating nuclear reactions and weather broadcasting, for example.
"You are also creating new functionality," says Nalamasu. "Such technology has vast implications, for example, integrating biochips with silicon chips. The wonderful thing is that if we adopt this technology, we'll develop things we can't even envision today."
"Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?" - Patrick Henry
There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways.
Please help metamoderate.
They do already do this... Intel chips have more than 7 layers on them. They arent really stacked wafers either; the film-growing, dopant implanting, CMP, and other processes can be repeated many times on the same wafer.
Didn't RTFA, but obviously this must be more than just the usual layering.
The current 7+ layer chips are talking about metalization layers. Wires, in other words. There is only one layer of transistors, which is at the top of the silicon substrate. I am not aware of any production process which has multiple layers of transistors.
People have been trying to build 3-D ICs for a long time because of the obvious benefits. The article describes a process of bonding multiple wafers in a stack, with wires going between the levels. Sounds to me like it would work, but it would only make the heat dissipation problem worse than it already is. My guess is 3-D chips will be used for low-power devices initially.
TTFN
There are a lot of hurdles that this document doesn't really get into. It does mention manufacturing but here are some hard core items that need to be considered. 1. Yield goes as e^(-alpha * A) where A is your area and alpha is your yield coefficient. So if you have non-yielding chips on one wafer and you mate it to another wafer that also has non-yielding chips, your total yield goes down at somehting like Y^L where L is the number of layers and Y is the yield given above and Y is 1. So if your yield is 75% and you have 5 layers then your final yield will be only 23%. 2. Testing. If a whole wafer is bad and you put it in your stack of chips, all the chip stacks will be bad. It would be best to test before you put those wafers together. Thats not easy. 3. Packaging is a big issue. Will it be standard wire bonding or something else. Does this thing really generate a lot less heat? And are the interconnects really a lot shorter. If the chip to chip connects cost the same as inter die vias then maybe so but my guess is that those chip to chip connections are a lot more expensive and take a lot more area than vias within the same chip. And alignment of one wafer to the next is also an issue along with getting good interconnect all the way through those stacks. Anyway, those are some thoughts. Its clear to me that 3D chips are a long way off and have there place in very specialized applications in the near term due to the complexities mentioned above. Wardini
I'd like to thank the author, Spy der Mann, for having the foresight to make a coral cache of the site before posting. Kudos to you, mate.
Didn't Gene Amdahl blow a fortune trying to do this 20+ years ago? I think the company was Trilogy. They did succeed in some die stacking technology but I think they ended up selling the ideas and it went nowhere.
They won't manufacture these things at such a level that they become a cube anytime soon. Each layer is very small (think the micrometer (1/1000 of a millimeter) scale or smaller), and based on the article they're talking about using 3 layers.
The majority of the height of a typical chip is the external packaging, so adding 3 or even 50 layers is unlikely to result in a noticable increase in width, so heat sink design remains unchanged.
Sure the heat would increase if you don't change the design, but no one would do this. See layers for more info.
The benefits to this are huge. Lets say can put down 4 layers or transistors instead of 1. If you were making a processor, you could use 3 of the layers for L2 cache (or L1 cache even), and you could potentially have 9MB of cache (1mb for half layer). Already about half of the die space on modern processors is used for L2 cache, so this would result in a huge performance increase with no redesign.
But realistically no one would do this with current technology as the cost of the processor would increase by a factor of 4 or more.
Another more useful example is taking the 100 billion or so transistors on a processor, and using 1/4th the area by splitting them up in 4 layers. This results in a smaller chip which means a smaller end device.
Combine this with the current pace of miniturization, and you might just surpass Moore's law.
Some Information on Layers: A typical processor or chip is made with a transistor layer, followed by layers of wires (9+ on some intel chips). Being able to stack layers of transistors allows for a huge increase in transistor density, and more efficient designs (less wire = less resistence = less heat). If there is less heat, you can clock the processor higher
Disclaimer: Some of this information may be incorrect or outdated as I've only taken 1 VLSI course, and designed only 1 processor.
It's all interrelated.
.
,Power can also be defined as :
The basic Power equation (in Watts) is Volts times Amps (V*I)
Aha! But from Ohms law, Volts is Amps times Resistance (V=I*R). And Amps is Voltage over resistance (I=V/R).
So substituting back into the original equation
P = (I*R)*I = I^2R
P = V*(V/R) = V^2R
So you can hopefully see from all that mess, any change of voltage,current,resistance will change power dissipated.
You are in a twisty maze of processor lines, all alike.
There is a lot of hype here.
wow... that's so wrong.
/. tutorial on power line transmission. For more basic information, along with images, check the howstuffworks article on power distrobution: http://science.howstuffworks.com/power.htm
resistance is like the size of a pipe that water is flowing through, consider voltage like water pressure and the current like the flow of the water. the smaller the pipe is, the more pressure you need to pass the water through at the same speed.
For the next blurb to make sense, I need to say that while transformers step up Voltage, the power calc is the same on both sides of it (V*I on one side == V*I on other side)
Power lines are actually really low impedance (resistance in AC) wires, but due to their astounding length they have pretty high resistance. To reduce power loss in power lines, the electrical companies step up the Voltage using a transformer. They do this because if you up the voltage in the middle step, (the power lines) the loss in power is much less, as the current delivered to the end user is much less than that going through the lines.
Thus ends your
Yield: When you stack 4 layers up, the only economical way would be to test the four layers separately before stacking. Testing means that you would need pull the signals out before you can do that. You will lose some of the wirelength reduction advantage there because you will now have to design the system for intermediate testing. No, testing after all packaging is not a viable option. Do a simple calculation, if probability of one layer working is 0.99, then probability of 4 layers working simultaneously will be (0.99)^4 = 0.96. This will significantly affect your cost.
Bigger L2 onchip cache: Actually that may not help that much. If you have ran the SPEC2000 or latest benchmarks, too large a L2 cache doesn't help. Yes SPEC benchmarks are not the real world applications. But making L2 bigger also means larger access time. In the end you may end up not gaining anything. A more interesing idea would be to put on-chip main memory. Again the major latency is not due to its being off-chip but due to memory architecture design itself. The only overhead you will save by bringing main memory on chip will be the multiplexing of signals and buffers. That is a small fraction of the off-chip memory latency. The main bottleneck is still the access from the rows and banks.
Is it really 3D ?: Actually it is not really 3D as you cannot connect two layers where you want. Due to technology problems, the interlayer connections are much bigger than rest of the features. They also have lot of electrical resistance. For example RPI technology requires interlayer interconnects to be 4-6 microns wide with 4-6 microns distance. That is a lot of real estate on chip if you consider that transistor gate length in production is 90 nm. So there is a long way to go.
Is 3D useful for microprocessor? That is still a debate. But there is somewhere else it may be useful: heterogenous integration. If you want to integrate RF, Analog and Digital: you can make them separately and optimize them separately. In the end you stack them up and that seems to be more promising application.
I always thought it was the resistance that caused heat and not the current. Anybody got any links that demonstrate what the correct situation is?
(The following is extremely simplified, and ignores alternating voltages, capacitive and inductive effects).
Two equations:
U = I*R (Ohm's law)
and
E = U*I
E is the heat energy
U is the voltage
I is the current
Now, it depends on your situation. If your power source is constant voltage (or, in more engineering terms, it has low internal resistance, for example mains power), U is pretty much constant. The current through a load is then determined by the resistance of the load (using equation 1). The amount of heat you get is then proportional to the current, and inversely proportional to your resistance. So, if you plug in a heater to the wall, the lower the resistance of the heating coil, the more current flows through the circuit and the more heat energy you get.
A less perfect voltage source (say, a battery) has significant internal resistance; the more current you extract from it, the more its voltage drops. Your first equation becomes U = I*(R+r), with R being the internal resistance of your battery. You'll get most power from this setup when the resistance of your load equals the internal resistance. At this point, the heat generated in the battery is equal to the heat generated in the external load.
And, for fun, you can also build current sources, that force a certain current through any load you connect to them (within limits, of course). They do this by changing their output voltage to match the resistance of the load. There are *many* uses for such sources in electronic devices.
3-D chips do decreases wire length, according to the thesis and the IEEE paper in the links below, 56% less interconnect is required for a 5 layer chip. Wafer bonding has been thoroughly investigated, and processes compatible with standard CMOS have been found and will soon find a use in memory (I'm sure I read something about a start-up stacking chips for memory, I think it was called Tezzaron).
d csg/publications.html
I EEE.pdf
:-)
http://www-mtl.mit.edu/researchgroups/icsystems/3
http://www.stanford.edu/class/ee311/NOTES/3DProc_
The big problems facing the industry are the lack of good design tools and the issues associated with yield and heat. Design tools will be developed as the processes become more refined. Yield issues and heat will likely need to be taken into consideration in the design. Consider if you have an 80% yield on each wafer; when you have 5 layers of silicon--assuming defects are not correlated to the location on the chip, and no defects due to the bonding process--your yield reduces to 33%. Of course, we are able to have more redundancy with more silicon layers, so we can design systems that are fault tolerant (google: fault tolerant architectures. lots of good stuff). The costs of the chips will probably direct represent the decrease in yield -- good designs and tools will likely save companies a lot of money (i shouldn't give away my secrets before i patent them
Cooling the higher density chips is probably the most major hurdle towards development of 3-D circuits. A few of these documents hint that microfluidic cooling systems may be the solution. Georgia Tech researchers made an advance on this end a few weeks ago by presenting a microfluidic manufacturing process compatible with standard CMOS design:
http://www.physorg.com/news4657.html
Expect lots of great things in the years to come. For now you can probably expect 3-D integration to creep into specialty mixed signal chips that are extremely expensive, and memory where heat generation is less of a problem. Microfluidic cooling technologies will be adopted in the near term for 2-D high power chips. The first 3-D micro-processor architectures will probably use extra layers for clock distribution, global interconnect systems, and power distribution systems. Caching systems will likely be added to as a third layer until new design approaches (and better tools) allow for the design of multi-layer integration with logic interspersed between the layers.
I'm not sure I understand what you're looking for, but if you simply want the heat as a function of current and resistance, then replace U in equation 2 and you'll get
There you go; you can verify the formula experimentally; double the current and watch the heat output increase four times. It's easiest if you have a calorimeter, but it should be easy to improvise a desktop setup sufficient for a qualitative verification.
"Power" is the measure of energy per time unit ( that is, P = E/t ).
The heat dissipation is directly proportional (by a material-specific constant) with that energy (E), which is
E = P*t = V*I*t = V^2*t/R
As mentioned before, the heat dissipation wont' drop because the resistence is lower, but because that lower resistance allows a similar drop in voltage, and E depends on the square of V
gtkaml.org
In your frankfurter experiment, The voltage was the same across each of the dogs and so the only thing that was different was the current as a result of the conductivity of the sausages. In this case, P = VI = V^2/R for each of the dogs.
If you had connected the hot dogs in series, like this:You would create a voltage divider network. The analysis for which goes like this: The current through any loop in the circuit is constant (e.g. the same current would be going through both the dogs, but the voltage supply would "see" a higher overall resistance so the total current would be less than in either case.)
In this case, the largest voltage drop is across the higher resistance. since the current is the same through both, the generic dogs will dissipate the most heat in this isntance.
Imagine cutting the generic dog to a length that made it less resistive than the ballpark. In this case, the total current would increase from the previous, and the ballpark would have the large voltage drop.
A simple power supply regulator does just that: it puts a resistance in series with the load and adjusts that resistance so that the voltage across the load is the same no matter the load. This presents some serious efficiency issues when the unregulated voltage is significantly greater than the desired voltage.
In fact, the IC is more complicated than that, introducing parallel and series parallel circuits, and transconductance elements, capacitance and even quantum tunnelling, but suffice to say, in general, the lower the wire resistance, the lower the fraction of heat disipated by the wires themselves.
Can you be Even More Awesome?!