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Researchers Create 3-Dimensional Chips
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
I remember there were tests using diamond deposited on chips as a strong heat conductor. The whole point was to help make multilayered chips possible. Haven't read anything lately but it sounded promising.
See: Thermal Conduction Module: A High-Performance Multilayer Ceramic Package
Chip H.
I have to correct you. Since I = V/R where I is the current in amperes, V is the voltage, and R is the resistance in ohms, less resistance means more current. Current is what creates heat and gets work done. Resistance isn't friction, it's simply the volume of electron flow possible through any given medium. Your observation that there would be more resistance was correct, however it would result in more heat. Take basic high school physics before youn try to work that out again. I would know - we did a demonstration in which two different types of hot dogs were used as resistors. Generic brand hot dogs had much more resistance and didnt do much. Ballpark hot dogs OTOH had less and started to smoke within minutes. Also, if you look on the inside of you computer all those little resistors have thousands to millions or more ohms or resistance.
I am Spartacus
None of this is relevant in the long run. Eventually, chip manufacturers will hit the blank wall of the Heisenberg Uncertainty Principle. As you try to cram more transistors into smaller spaces (even in 3-D), you localize the electron wavefunctions (not to mention that cuttoff is achieved only if the electrons are in conduction bands, which will cease to exist if the transistors are too small). This means that they delocalise in Momentum space, and their Shannon entropy goes up, causing them to heat up drastically and eventually melt. Solid State Technology has taken us far enough, trying to stack chips will only prolong the inevitable. Researchers should focus on a fundamentally new method of computation, like using entangled Greenberger-Horne-Zeilenger states or Bell states for computational purposes.
l'Homme n'est Rien l'Oeuvre Tout: Gustave Flaubert to George Sand
This is an area that I actually know something about. I have an advanced degree in VLSI circuit design and have studied details of today's IC fabrication process.
First of all, the title is incorrect. RPI hasn't "created" anything. From what I read in the highly theoretical article, the only thing that Lu has done is start a program at RPI to look into stacking wafers. Granted, procuring funding for an IC fabrication research is phenomenal news given the exorbitant cost of the facilities! But this article serves no other purpose than to promote a new VLSI research program.
The concept of stacking ICs vertically is nothing new! The idea has been completely obvious since we started running out of room in the 2-dimensional plane. The root problem, and the one that Lu hopes to solve, is that IC fabrication is a highly complex chemical process. The bare Si wafers go through dozens of processing steps where liquids and gasses are deposited and then removed using masks accurate to the nanometer. Layer upon layer of accurately doped Si is added to yield the perfect consistency of impurities (usually Boron or Phosphorous). This gives the wafer its p-n junctions: the crux of every transistor and active circuit element. Multiple layers of polysilicon (a substitute for metal due to the improved accuracy in placement), and metal (usually alluminum) are used for interconnecting the active and passive devices created in the base silicon. The final layer deposited is a several micron-thick glass that serves to protect the wafer's ICs from any chemicals exposed to the wafer post-manufacturing. This is a severely minimalistic description of how ICs are created, but I think you get the picture of how difficult it is and why it costs so much.
The thing is, after the numerous layers of Si, Al, and SiO2 are deposited, the surface is extremely "rough and bumpy" for lack of a better word.
If you were to place the active regions of more transistors on top of all this stuff, your Xistors are almost guaranteed never to *all* be working. It is extremely difficult to expose the several nanometer wide interconnect from one layer through the glass. On all ICs, this is done on very large metal pads that are on the outer edges of the layout. In order to decrease the path length from one wafer layer to the next, this pad must be somewhere over the circuit, which is currently not feasible!
I'm curious how Lu theorizes he is going to slap 3 glued wafers together while guaranteeing proper interconnections. This is a problem we've been trying to solve for quite some time. Alas, the article doesn't state any of this useful information.
I was excited when I read the title, but this article doesn't deserve the headline on the front page of slashdot, IMHO.
On a less critical note, I'm confident that Lu (or any of the many other semiconductor researchers in the world) will eventually make progress toward 3-dimensional fabrication. Unfortunately, I don't see this happening for at least a decade. Even more unfortunate is that the cost of 3-dimensional stacking won't be cost effective for customers of ICs for quite some time (~20-30 years!). I wish Lu and his competitors all the luck that they'll need in this area.
I am NOT putting my signature in this stupid little box! How do I know you won't steal my identity???
Seymour Cray with the Cray 3 had his processor bricks made of Gallium arsenide. The wikipedia article has flaws (I'll try to fix later) but it has the point that he went down the route of the 3d chip and circuitry much earlier than this /. story.
A brilliant man, Seymour...
Do you know why the road less traveled by is littered with the bones of the unwary?
PSI is almost upon us.
FYI: PSI is a tale I spun in the '70s or so, when Large Scale Integration (LSI - eventually with a company named after it) and Very Large Scale Integration (VSLI) were industry buzzwords for ICs with a higher level of integration than a single-digit count of gates or flops to be externally interconnected.
PSI would involve:
- constructing a 3-D "chip"
- using ion beam epitaxy and doping to build it up in layers
- testing as you go using electron beams for power and signal injection and higher-voltage electron beams for "positive" voltage injection and as test prods (using secondary emission to pull more electrons than they insert and/or to read the voltage on the chip's internal nodes)
- turning up the beam current to vaporize (and later rebuild correctly) any defective component so the whole thing ends up flawless despite its large gate count. (100% yield!)
- using diamond for the semiconductor (mainly for its stability and heat conduction properties)
- running it in an inert atmosphere (so it can get up to red-hot without burning up or converting into graphite)
- building it as an approximate cube - up to, say, 6 feet on a side
- powering and cooling it on two opposing faces
- with water-cooled silver bus-bars the size of the faces
- connecting it by covering the other four faces with optic fibers for I/O (to interconnect with integrated light-emitting and sensing devices).
Of course the point of the yarn, in addition to potentially being possible, is the appearance of the resulting device:
An enormous supercomputer in the form of a 6-foot cube of diamond, glowing slightly red from operating heat, supported by water-cooled silver bus bars in an inert atmosphere within a glass bottle (ala a vacuum tube), with millions of optic fibers to provide it with sufficient I/O.
Just the sort of thing you'd find as a component in, say, one of the later Skylark spacecraft of E. E. (Doc) Smith's Golden-age SF stories.
Bantam Dominique roosters crow a four-note song. Once you've heard it as "Happy BIRTHday" you can't NOT hear it that way
In the short term, expect to see a lot of failed wafers. The alignment problems between different fabricated wafers are going to make the interconnectors mismatch and fail under stress, or as manufactured junctions "creep", especially under thermal load. Also expect to see some nasty behavior with capacitive or inductive coupling between transistors which are vertically on top of each other, instead of merely adjacent. Groundplane, groundbounce, and other related issues are about to take a quantum leap in complexity with this approach.