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Researchers Create 3-Dimensional Chips
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
It all depends on density of the transistors. You can squeeze 1 square mile into a 1 inch cube, but it will take 334,540,800 individual layers to do so.
Well, thye haven't been doing it ALL along, but they've been doing it more more than a couple years already.
P4's currently run on a 7 layer design and AMD 64's run between 4 and 9 layers depending on the specific model.
I'm sure IBM does the same also.
The key difference between a Programmer and a Senior Programmer is that one of them is Mexican.
This is really cool stuff. Essentially they're making silicon wafers smaller by removing all the silicon in the substrate after the wafer is fabbed. Then they can put this few-micron-thick layer onto another fabbed wafer - perhaps made with a different process - then they can repeat the process. This allows sensor, analog, processor and memory to be made in the best processes for each function but with communication channels tens of thousands of wires wide and only microns long.
This article is worth reading - this is going to be huge. Also there is a really fantastic picture of a see-through microprocessor wafer with the article.
From the article:
Wafer-level stacking also allows for short connections between different types of chips. "Particularly today the industry is trying to combine memory with the processor, and more than half of the chip is taken up by memory," Lu explains. "When we stack layers, we have a processor on the bottom and layer the memory on top, with a short access time between them." Lu says the reduction of memory access time would be a huge advancement for large-scale computer clusters calculating nuclear reactions and weather broadcasting, for example.
"You are also creating new functionality," says Nalamasu. "Such technology has vast implications, for example, integrating biochips with silicon chips. The wonderful thing is that if we adopt this technology, we'll develop things we can't even envision today."
"Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?" - Patrick Henry
There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways.
Please help metamoderate.
They do already do this... Intel chips have more than 7 layers on them. They arent really stacked wafers either; the film-growing, dopant implanting, CMP, and other processes can be repeated many times on the same wafer.
Didn't RTFA, but obviously this must be more than just the usual layering.
The current 7+ layer chips are talking about metalization layers. Wires, in other words. There is only one layer of transistors, which is at the top of the silicon substrate. I am not aware of any production process which has multiple layers of transistors.
People have been trying to build 3-D ICs for a long time because of the obvious benefits. The article describes a process of bonding multiple wafers in a stack, with wires going between the levels. Sounds to me like it would work, but it would only make the heat dissipation problem worse than it already is. My guess is 3-D chips will be used for low-power devices initially.
TTFN
There are a lot of hurdles that this document doesn't really get into. It does mention manufacturing but here are some hard core items that need to be considered. 1. Yield goes as e^(-alpha * A) where A is your area and alpha is your yield coefficient. So if you have non-yielding chips on one wafer and you mate it to another wafer that also has non-yielding chips, your total yield goes down at somehting like Y^L where L is the number of layers and Y is the yield given above and Y is 1. So if your yield is 75% and you have 5 layers then your final yield will be only 23%. 2. Testing. If a whole wafer is bad and you put it in your stack of chips, all the chip stacks will be bad. It would be best to test before you put those wafers together. Thats not easy. 3. Packaging is a big issue. Will it be standard wire bonding or something else. Does this thing really generate a lot less heat? And are the interconnects really a lot shorter. If the chip to chip connects cost the same as inter die vias then maybe so but my guess is that those chip to chip connections are a lot more expensive and take a lot more area than vias within the same chip. And alignment of one wafer to the next is also an issue along with getting good interconnect all the way through those stacks. Anyway, those are some thoughts. Its clear to me that 3D chips are a long way off and have there place in very specialized applications in the near term due to the complexities mentioned above. Wardini
I'd like to thank the author, Spy der Mann, for having the foresight to make a coral cache of the site before posting. Kudos to you, mate.
It's all interrelated.
.
,Power can also be defined as :
The basic Power equation (in Watts) is Volts times Amps (V*I)
Aha! But from Ohms law, Volts is Amps times Resistance (V=I*R). And Amps is Voltage over resistance (I=V/R).
So substituting back into the original equation
P = (I*R)*I = I^2R
P = V*(V/R) = V^2R
So you can hopefully see from all that mess, any change of voltage,current,resistance will change power dissipated.
You are in a twisty maze of processor lines, all alike.
There is a lot of hype here.
wow... that's so wrong.
/. tutorial on power line transmission. For more basic information, along with images, check the howstuffworks article on power distrobution: http://science.howstuffworks.com/power.htm
resistance is like the size of a pipe that water is flowing through, consider voltage like water pressure and the current like the flow of the water. the smaller the pipe is, the more pressure you need to pass the water through at the same speed.
For the next blurb to make sense, I need to say that while transformers step up Voltage, the power calc is the same on both sides of it (V*I on one side == V*I on other side)
Power lines are actually really low impedance (resistance in AC) wires, but due to their astounding length they have pretty high resistance. To reduce power loss in power lines, the electrical companies step up the Voltage using a transformer. They do this because if you up the voltage in the middle step, (the power lines) the loss in power is much less, as the current delivered to the end user is much less than that going through the lines.
Thus ends your
Yield: When you stack 4 layers up, the only economical way would be to test the four layers separately before stacking. Testing means that you would need pull the signals out before you can do that. You will lose some of the wirelength reduction advantage there because you will now have to design the system for intermediate testing. No, testing after all packaging is not a viable option. Do a simple calculation, if probability of one layer working is 0.99, then probability of 4 layers working simultaneously will be (0.99)^4 = 0.96. This will significantly affect your cost.
Bigger L2 onchip cache: Actually that may not help that much. If you have ran the SPEC2000 or latest benchmarks, too large a L2 cache doesn't help. Yes SPEC benchmarks are not the real world applications. But making L2 bigger also means larger access time. In the end you may end up not gaining anything. A more interesing idea would be to put on-chip main memory. Again the major latency is not due to its being off-chip but due to memory architecture design itself. The only overhead you will save by bringing main memory on chip will be the multiplexing of signals and buffers. That is a small fraction of the off-chip memory latency. The main bottleneck is still the access from the rows and banks.
Is it really 3D ?: Actually it is not really 3D as you cannot connect two layers where you want. Due to technology problems, the interlayer connections are much bigger than rest of the features. They also have lot of electrical resistance. For example RPI technology requires interlayer interconnects to be 4-6 microns wide with 4-6 microns distance. That is a lot of real estate on chip if you consider that transistor gate length in production is 90 nm. So there is a long way to go.
Is 3D useful for microprocessor? That is still a debate. But there is somewhere else it may be useful: heterogenous integration. If you want to integrate RF, Analog and Digital: you can make them separately and optimize them separately. In the end you stack them up and that seems to be more promising application.