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Researchers Create 3-Dimensional Chips
Spy der Mann writes "Professor James Lu and other researchers of the Rensselaer Polytechnic Institute, managed to create three-dimensional chips (coral cache) to optimize the design of future processors and prevent overheating. "Make the interconnect wire shorter, and you cut the delay time," says Lu. "A simple way to make them shorter is to stack the transistors.""
Hopefully there will be a parallel advance in cooling technology.
Karma: -2147483648 (Mostly affected by integer overflow)
Flat chips suck. These chips have flavor ridges(tm).
I thought they'd been doing this all along.
Guess I was just ahead of my time...in my head.
We complain about all the /. stories that are dupes but don't give proper credit to the editors when a non-dupe makes it past their radar.
Propz to Timothy for posting an original article! Keep up the good work!
It all depends on density of the transistors. You can squeeze 1 square mile into a 1 inch cube, but it will take 334,540,800 individual layers to do so.
Want to write a time travel game. Or maybe I already did.
Already been done.
I read in a paper recently where scientists have had some success in developing a four-dimensional transistor by using nanotubes to set up a quantum Klein bottle wherein the current passes through Bohr space and thus runs parahybolically.
In practice, you should actually be able to use this method to set up any n-dimensional transistor, provided you can find a sufficiently clean source of power. Modern power supplies have heretofore been plagued by an excess of static dissonance.
Essentially, they say this packs it denser. And a cube vs a flat processor = less surface/transistor. I see only factors which makes this *harder* to cool. Maybe someone can explain...
Kjella
Live today, because you never know what tomorrow brings
This is really cool stuff. Essentially they're making silicon wafers smaller by removing all the silicon in the substrate after the wafer is fabbed. Then they can put this few-micron-thick layer onto another fabbed wafer - perhaps made with a different process - then they can repeat the process. This allows sensor, analog, processor and memory to be made in the best processes for each function but with communication channels tens of thousands of wires wide and only microns long.
This article is worth reading - this is going to be huge. Also there is a really fantastic picture of a see-through microprocessor wafer with the article.
From the article:
Wafer-level stacking also allows for short connections between different types of chips. "Particularly today the industry is trying to combine memory with the processor, and more than half of the chip is taken up by memory," Lu explains. "When we stack layers, we have a processor on the bottom and layer the memory on top, with a short access time between them." Lu says the reduction of memory access time would be a huge advancement for large-scale computer clusters calculating nuclear reactions and weather broadcasting, for example.
"You are also creating new functionality," says Nalamasu. "Such technology has vast implications, for example, integrating biochips with silicon chips. The wonderful thing is that if we adopt this technology, we'll develop things we can't even envision today."
"Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?" - Patrick Henry
There is, sort of. If the wires are shorter, they have less resistance end-to-end assuming they have the same thickness, are made from the same material, etc etc. Less resistance means less heat (and maybe core voltage could be lowered slightly too, since there would be less of a voltage drop). However, I honestly don't know how much heat comes from the actual junctions versus circuit pathways.
Please help metamoderate.
There must be a new meaning of the word "simple" that I'm not familiar with.
Mea navis aericumbens anguillis abundat
See: Thermal Conduction Module: A High-Performance Multilayer Ceramic Package
Chip H.
"We've gone beyond zero insertion force -- you just throw the cubes into the enclosure and they will connect," said an Intel spokesman.
According to the spokesman, the functionality of the system will depend on the orientation of the chips as they land in their respective sockets. If the chips land on 7 or 11, Windows will run; 2, 3, or 12 produces the Blue Screen of Death. Similarly, any other number will produce an exception unless it is thrown again before a 7.
There are a lot of hurdles that this document doesn't really get into. It does mention manufacturing but here are some hard core items that need to be considered. 1. Yield goes as e^(-alpha * A) where A is your area and alpha is your yield coefficient. So if you have non-yielding chips on one wafer and you mate it to another wafer that also has non-yielding chips, your total yield goes down at somehting like Y^L where L is the number of layers and Y is the yield given above and Y is 1. So if your yield is 75% and you have 5 layers then your final yield will be only 23%. 2. Testing. If a whole wafer is bad and you put it in your stack of chips, all the chip stacks will be bad. It would be best to test before you put those wafers together. Thats not easy. 3. Packaging is a big issue. Will it be standard wire bonding or something else. Does this thing really generate a lot less heat? And are the interconnects really a lot shorter. If the chip to chip connects cost the same as inter die vias then maybe so but my guess is that those chip to chip connections are a lot more expensive and take a lot more area than vias within the same chip. And alignment of one wafer to the next is also an issue along with getting good interconnect all the way through those stacks. Anyway, those are some thoughts. Its clear to me that 3D chips are a long way off and have there place in very specialized applications in the near term due to the complexities mentioned above. Wardini
I'd like to thank the author, Spy der Mann, for having the foresight to make a coral cache of the site before posting. Kudos to you, mate.
It's all interrelated.
.
,Power can also be defined as :
The basic Power equation (in Watts) is Volts times Amps (V*I)
Aha! But from Ohms law, Volts is Amps times Resistance (V=I*R). And Amps is Voltage over resistance (I=V/R).
So substituting back into the original equation
P = (I*R)*I = I^2R
P = V*(V/R) = V^2R
So you can hopefully see from all that mess, any change of voltage,current,resistance will change power dissipated.
You are in a twisty maze of processor lines, all alike.
There is a lot of hype here.
wow... that's so wrong.
/. tutorial on power line transmission. For more basic information, along with images, check the howstuffworks article on power distrobution: http://science.howstuffworks.com/power.htm
resistance is like the size of a pipe that water is flowing through, consider voltage like water pressure and the current like the flow of the water. the smaller the pipe is, the more pressure you need to pass the water through at the same speed.
For the next blurb to make sense, I need to say that while transformers step up Voltage, the power calc is the same on both sides of it (V*I on one side == V*I on other side)
Power lines are actually really low impedance (resistance in AC) wires, but due to their astounding length they have pretty high resistance. To reduce power loss in power lines, the electrical companies step up the Voltage using a transformer. They do this because if you up the voltage in the middle step, (the power lines) the loss in power is much less, as the current delivered to the end user is much less than that going through the lines.
Thus ends your
Seymour Cray with the Cray 3 had his processor bricks made of Gallium arsenide. The wikipedia article has flaws (I'll try to fix later) but it has the point that he went down the route of the 3d chip and circuitry much earlier than this /. story.
A brilliant man, Seymour...
Do you know why the road less traveled by is littered with the bones of the unwary?