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Intel Plans to Overhaul Chip Architecture
Carl Bialik from the WSJ writes "Intel is planning to announce an entirely new chip architecture later this month at the company's developer forum, the Wall Street Journal reports. The company isn't discussing details yet, but it's expected that Paul Otellini will discuss a 'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'"
One thing the article didn't make clear is what exactly Intel means by "A New Chip Architecture". i.e. Do they mean a new architecture as in the Itanic (but low power!), or a new chip architecture as in, "We're ditching the 20 stage pipeline in exchange for a more reasonable 6 stage pipeline, swapping out most of the control circuts for those from our StrongARM line, and rewriting the microcode to execute all of the Pentium instructions on a simple, low power RISC core."
While they could go either way, I hope they've learned from the Itanium and EM64T debacles that they should stick with a compatible microcode. Leave the super-instruction sets to the MIPS and SPARCs of the world.
Javascript + Nintendo DSi = DSiCade
Conroe according to Anandtech...4 92
http://anandtech.com/cpuchipsets/showdoc.aspx?i=2
HJ
This is kinda funny in two ways..
'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'
Not overheard anywhere: "We are peeking through a knothole in AMD's fence and seeing what they are up to.
Nitpick: "The company isn't discussed details yet"
The proper word is ain't.
A feeling of having made the same mistake before: Deja Foobar
No... I doubt they'll be using the Pentium M core for this redesign. The new push will be for multithreading. The pipeline may shrink a bit, but long pipelines are nice because they allow for very high clock speeds due to low fanouts. When designing high power software going from 4 threads to 16 is often not too difficult. At least if you use the right paradigms. Combined with low-latency communication (L2 cache speeds) this makes for a very powerful combination.
.. . many of them don't need more power than what a simple 4GHz core can offer them. Those that require more computation than that will likely be reprogrammed to support multi-threading.
When designing such a machine its important to consider what the software will look like. Is it better to run 16 threads each with a CPI (cycles per instruction) of 1.2 or run 32 threads with a CPI of 1.6? This will actually push us much further back than the P3.
The cores on these processors are far more likely to resemble the original Pentiums. Simple pipelines, in-order execution, minimal instruction level parallelism. When the current P4 superscalar beasts can rarly pull a CPI of 1, whats the point of allowing 4 instructions to execute simultaneously (at least if the core is only executing one thread).
The new push will be to have 8 very simple cores (albeit with advanced SSE4 units with even wider vector instructions such as 256 or 512 bits) and allow each core to run 2 or 4 threads. This won't be hyperthreading as hyperthreading is a form of SMT (although Intel may reuse the name). It will be a form of fine-grained multithreading that allows context switches on L1 or L2 cache misses, as well as other latent operations. Of course their will also be logic to allow all the threads to run equally.
With these processors we'll be able to run 16-32 threads simultaneously (or almost simultaneously). For applications that can be massively threaded this will result in a huge boost in performance. For the single threaded applications that aren't easily parallelizable
This technology will scale tremendously. These new processors will essentially be supercomputers on a chip. I think this because of a presentation I saw by one of the lead P4 architects who was talking about future processors. This will be the future, and the time is now to rethink any applications you currently have and find someone competent in multithreading.
Phil