Intel Plans to Overhaul Chip Architecture

Carl Bialik from the WSJ writes "Intel is planning to announce an entirely new chip architecture later this month at the company's developer forum, the Wall Street Journal reports. The company isn't discussing details yet, but it's expected that Paul Otellini will discuss a 'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'"

Comments

What does this mean?

[AKAImBatman]

One thing the article didn't make clear is what exactly Intel means by "A New Chip Architecture". i.e. Do they mean a new architecture as in the Itanic (but low power!), or a new chip architecture as in, "We're ditching the 20 stage pipeline in exchange for a more reasonable 6 stage pipeline, swapping out most of the control circuts for those from our StrongARM line, and rewriting the microcode to execute all of the Pentium instructions on a simple, low power RISC core."

While they could go either way, I hope they've learned from the Itanium and EM64T debacles that they should stick with a compatible microcode. Leave the super-instruction sets to the MIPS and SPARCs of the world.

Re:What does this mean?

[dbrutus]

I have a hunch that Steve Jobs knows. Apple goes to Intel during the 2006-2007 time frame because of their low power consumption chips out there on their roadmap. Now Intel is launching low power consumption chips. I would be shocked if Apple didn't have access to early chips as a condition for switching architectures.

It's Conroe

[Hack Jandy]

Conroe according to Anandtech...
http://anandtech.com/cpuchipsets/showdoc.aspx?i=24 92

HJ

Announcement

[Ryan Stortz]

Who wants to bet that the announcement includes a integrated memory controller? I wouldn't be suprised if they just licenced Opteron technology from AMD; it would be alot cheaper than developing their own. Although, they could always just outright steal it.

Not a user-perceptable change.

[sbaker]

On NPR this morning, they mentioned that Intel had said that a typical PC user wouldn't notice any change as a result of this new architecture. So one presumes this means no major instruction set revisions or anything.

Re:Not a user-perceptable change.

[ArsonSmith]

When Apple said they would switch to intel what they didn't say was that Intel was switching to PPC.

totally cool

[ackthpt]

no-way-the-old-architecture-is-totally-cool

This is kinda funny in two ways..

• 1. Intel often comes out with new processors which run HOT, pushing the chip to extremes of physics.
• 2. The old architecture is a dinosaur, harkening back to the 8088 and rather inefficient in many respects, where RISC processors were supposed to trump it. Which is still around? It seems you can come up with all the technological advances you like, so long as it is still a pumped up 8088.

'technology foundation designed from scratch to improve energy efficiency and make it easier to add more than two processors.'

Not overheard anywhere: "We are peeking through a knothole in AMD's fence and seeing what they are up to.

Nitpick: "The company isn't discussed details yet"
The proper word is ain't.

AMD's dual core offering better than Intel's

[Anonymous Coward]

According to various preliminary benchmarks from The Tech Report, Tom's Hardware and AnandTech, AMD's desktop dual-core chips are significantly better than Intel's dual-core desktop offerings in terms of performance and power consumption. This is partly due to the fact that the AMD solution has a better inter-core communication architecture and lower memory latency.

Meanwhile, Intel's desktop dual core chips seem to offer much more aggressive pricing at this time. AMD's lowest price dual core chip, the X2 4200 is almost twice as expensive as Intel's lowest cost dual core processor. However, an interview with three AMD execs on PCPerspective.com claims that "AMD would eventually have lower priced Athlon X2 processors via the waterfall effect in the future".

They have to redeem themselves

[realmolo]

As we all know, the Pentium 4 is a pretty goofy, shlocky design. The Pentium M is good, but it's essentially a Pentium Pro. That's 10 years old.

Intle NEEDS to prove that they can still make a good x86 chip from "scratch".

Re:Obligatory obvious sighting

[99BottlesOfBeerInMyF]

One has to wonder if Apple had any 'insight' to these plans when they signed the deal.

Actually, it is pretty likely that Apple was given a full roadmap and a few engineers to explain the whole thing while in in discussions and under NDA. The real questions are did this have anything to do with Apple's decision, is this in response to the deal with Apple, or is this just coincidental.

Semantics

[frankie]

The word "multiprocessor" should be "multicore". They're talking about 4 or 8 cores on a single CPU, which might be nice for blades but not so useful for a laptop or a gamer.

And of course, Macheads note the phrase "performance per watt".

My guess is a new x86

[Sycraft-fu]

Though they may not want to admit it, Intel knows they've lost the 64-bit format war for desktops at least.

So probably what the are working on is a next gen x86 architecture. Those don't come out too often, usually the design one and just modify it for a number of years. It sounds like they are going to start using modifiations on their Pentium M for desktops, which is cool since it is efficient both thermally and in terms of what it does per clock, but there's a limited life to it and they know it. The Pentium M is something of a throwback to the P3, which itself is really based on the Ppro design.

So my guess is Intel figures it's time to unviel a new design for a core, but on x86 architecture.

Re:My guess is a new x86

[philipgar]

No... I doubt they'll be using the Pentium M core for this redesign. The new push will be for multithreading. The pipeline may shrink a bit, but long pipelines are nice because they allow for very high clock speeds due to low fanouts. When designing high power software going from 4 threads to 16 is often not too difficult. At least if you use the right paradigms. Combined with low-latency communication (L2 cache speeds) this makes for a very powerful combination.

When designing such a machine its important to consider what the software will look like. Is it better to run 16 threads each with a CPI (cycles per instruction) of 1.2 or run 32 threads with a CPI of 1.6? This will actually push us much further back than the P3.

The cores on these processors are far more likely to resemble the original Pentiums. Simple pipelines, in-order execution, minimal instruction level parallelism. When the current P4 superscalar beasts can rarly pull a CPI of 1, whats the point of allowing 4 instructions to execute simultaneously (at least if the core is only executing one thread).

The new push will be to have 8 very simple cores (albeit with advanced SSE4 units with even wider vector instructions such as 256 or 512 bits) and allow each core to run 2 or 4 threads. This won't be hyperthreading as hyperthreading is a form of SMT (although Intel may reuse the name). It will be a form of fine-grained multithreading that allows context switches on L1 or L2 cache misses, as well as other latent operations. Of course their will also be logic to allow all the threads to run equally.

With these processors we'll be able to run 16-32 threads simultaneously (or almost simultaneously). For applications that can be massively threaded this will result in a huge boost in performance. For the single threaded applications that aren't easily parallelizable .. . many of them don't need more power than what a simple 4GHz core can offer them. Those that require more computation than that will likely be reprogrammed to support multi-threading.

This technology will scale tremendously. These new processors will essentially be supercomputers on a chip. I think this because of a presentation I saw by one of the lead P4 architects who was talking about future processors. This will be the future, and the time is now to rethink any applications you currently have and find someone competent in multithreading.

Phil

It's called i860 :-)

[Jeremiah Cornelius]

The Itanium will be re-christened "Xeon failure edition".

Intel i860

The Intel i860 (also 80860, and code named N10) was a RISC microprocessor from Intel, first released in 1989. The i860 was (along with the i960) one of Intel's first attempts at an entirely new, high-end ISA since the failed Intel i432 from the 1980s. It was released with considerable fanfare, and obscured the release of the Intel i960 which many considered to be a better design. The i860 never achieved commercial success and the project was terminated in the late 1980s. No known applications of the chip survive and it is no longer manufactured.

Technical features

Intel i860 MicroprocessorThe i860 combined a number of features that were unique at the time, most notably its VLIW (Very Long Instruction Word) architecture and powerful support for high-speed floating point operations. The design mounted a 32-bit ALU along with a 64-bit FPU that was itself built in three parts, an adder, a multiplier, and a graphics processor. The system had separate pipelines for the ALU, adder and multiplier, and could hand off up to three instructions per clock.

One fairly unique feature of the i860 was that the pipelines into the functional units were program-accessible, requiring the compilers to carefully order instructions in the object code to keep the pipelines filled. This achieves some of the same goals as RISC microprocessor architectures, where complex microcode, a sort of on-the-fly compiler, was removed from the core of the CPU and placed in the compiler. This led to a simpler core, with more space available for other duties, but resulted in much larger code, with negative impact on cache hits, memory bandwidth, and overall system cost. As a result of its architecture, the i860 could run certain graphics and floating point algorithms with exceptionally high speed, but its performance in general-purpose applications suffered and it was difficult to program efficiently (see below).

All of the buses were 64-bits wide, or wider. The internal memory bus to the cache, for instance, was 128-bits wide. Both units had thirty-two 32-bit registers, but the FPU used its set as sixteen 64-bit registers. Instructions for the ALU were fetched two at a time to use the full external bus. Intel always referred to the design as the "i860 64-Bit Microprocessor".

The graphics unit was unique for the era. It was essentially a 64-bit integer unit using the FPU registers. It supported a number of commands for SIMD-like instructions in addition to basic 64-bit integer math. Experience with the i860 influenced the MMX functionality later added to Intel's Pentium processors.

Performance (problems)

Paper performance was impressive for a single-chip solution; however, real-world performance was anything but. One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to properly order instructions at compile time. For instance, an instruction to add two numbers will take considerably longer if the data is not in the cache, yet there is no way for the programmer to know if it is or not. If you guess wrong the entire pipeline will stall, waiting for the data. The entire i860 design was based on the compiler efficiently handling this task, which proved almost impossible in practice. While theoretically capable of peaking at about 60MFLOPS for the XP versions, hand-coded assemblers managed to get only about up to 40MFLOPS, and most compilers had difficultly getting even 10.

Another serious problem was the lack of any solution to quickly handle context switching. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and need them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second, an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU.

Versions, Applica

Re:It's called i860 :-)

[stripes]

Intel i860

OkiData had a short lived Unix workstation product line based around these. I used them for a while.

One fairly unique feature of the i860 was that the pipelines into the functional units were program-accessible, requiring the compilers to carefully order instructions in the object code to keep the pipelines filled.

Only the floating point pipeline was directly exposed. Your first two FMULADD got garbage as the result, the third got the result of the first FMULADD... I *think* it also had a mode with more conventional stalling if you tried to do a 2nd FMULADD before the first completed (or if you used the result register).

The i860 also had a mode where you it would execute two instructions per clock, but you had to pair one integer instruction with one floating point instruction in that mode (and the pairing was static, if you put two integer instructions in a row the CPU would fault with an illegal instruction fault).

Paper performance was impressive for a single-chip solution; however, real-world performance was anything but.

It outperformed it's contemparary SPARC and MIPS CPUs by a considrable margin in FP, and by a small margin in integer heavy code. It was competitave with the HP snake systems (HPPA). It predated the Alpha, and was badly outmatched when the Alpha finally came out.

One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to properly order instructions at compile time. For instance, an instruction to add two numbers will take considerably longer if the data is not in the cache, yet there is no way for the programmer to know if it is or not. If you guess wrong the entire pipeline will stall, waiting for the data.

That was extremely common at the time. The best the contemporary CPUs had was the IBM ROMP (pre-IBM POWER!) that had register scoreboarding so it didn't take a stall until the result register was used. It wasn't until five to seven years later that out-of-order CPUs were commercially available (and I can't remember who did them first, maybe the TI SuperSPARC? Or was it the MIPS R8000?)

Another serious problem was the lack of any solution to quickly handle context switching. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and need them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second, an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU.

It seemed of handling disk interrupts, mouse movement, and even the relatively tiny FIFO for SoundBlaster 16 audio out. Maybe this was more a problem in theory then in practice? Clearly the i860 never got far in the embedded space though, and this couldn't have possibly helped.

The i860 did see some use in the workstation world as a graphics accelerator. It was used, for instance, in the NeXTDimension, where it ran a cut-down version of the Mach kernel running a complete PostScript. In this role the i860 design worked considerably better, as the core program could be loaded into the cache and made entirely "predictable", allowing the compilers to get the ordering right. This sort of use slowly disappeared as well, as more general-purpose CPUs started to match the i860's performance, and Intel lost interest.

I think it was also used as part of the "geometry engine" on SGI's Reality Engine product. There were something like 4 per GE, and up to 4 GEs on a Reality Engine, which was pretty impressive in 1991ish, but other then having something like 196 bits of memory per pixel falls pretty far short of today's $100 graphics cards.

Re:Attempt to scare IBM

[AKAImBatman]

Itanium didn't kill Alpha/MIPS/Sun.

Yes it did. When the hype was at it peak, it was actually preventing companies (such as the one I was working at during that time) from looking into Sun solutions, and HP made its infamous decision to ditch the Alpha line of processors in favor of the upcoming Intanic line.

At that time, Sun machines held a reasonable partiy with Intel's offerings, and Alpha NT desktops simply flew. Pentium III (Coppermine) was still in the development phase, and SGI was barely hanging on thanks to their N64 and NT Workstation deals.