Branched Nanotubes Offer Smaller Transistors

Designadrug writes "Tiny tubes of carbon, crafted into the shape of a Y, could revolutionize the computer industry, suggests new research. The work has shown that Y-shaped carbon nanotubes are easily made and act as remarkably efficient electronic transistors - but the nanotransistors are just a few hundred millionths of a meter in size -roughly 100 times smaller than the components used in today's microprocessors."

Comments

Moore's Law.

[Quebec]

Each time some expert's saying that Moore's Law is about to hit a barrier,
there is something going on like those promising nanotubes.

Another one for Moore against those doomsday preacher like this one:
http://news.zdnet.com/2100-9584_22-5112061.html

Re:Moore's Law.

[slapout]

Hey, you could have your own law:

Quebec's law: "Each time some expert's saying that Moore's Law is about to hit a barrier,
there is something going on like those promising nanotubes."

Re:Moore's Law.

[LWATCDR]

Except one of the reason Moore's observation held is that ICs are so much easier to make then what they replaced. These new nanotubes may not scale to well for mass production.
Moore's law IS not a fundamental law of the Universe. It was an observation of a trend that has held up for a lot long than anyone expected.

Re:Moore's Law.

[Anm]

Actually.. the sizes mentioned in the Moore's Law barrier article you linked to roughly equate to the "a few hundred millionths of a meter in size" (2/100,000,000 meters == 20 nano-meters ~= 16 nanometers). Since the barrier is over a decade away, the two articles aren't in conflict, as much as you would like to hope.

Anm

Re:Moore's Law.

[fbjon]

There was an article in Sientific American about making chips much smaller by letting water flow between the imprinting laser lens and the silicon wafer. The water changes the refractive index, so the lens can be better utilized, as I understand it, and apparently it's not particularly difficult either, since existing 193nm lithography can be used, and even surpass the planned 157nm lithography tech. Here's another article with some links.

Re:Moore's Law.

[amliebsch]

Moore's law applies to transistor counts per square inch, not clock speeds. You're thinking of the "Law of Marketing."

Re:Moore's Law.

[oringo]

Do you even know what Moore's law is? Even a highschool student can tell you that it has nothing to do with the MHz speed of the silicon, although theoretically as the widths of the gates shrink you can run the logic faster. Moore's Law simply states that the density of silicon chips doubles every 18 month.
On a sidenote, Intel's Netburst archicture has turned out to be a failure to reliably increase the PERFORMANCE of the CPU (ironically I'm using one right now), precisely because of the architecture's emphesis on higher clock rate. But other architectures, such as AMD64 and Power are rapidlly shrinking their die and consistently increasing performance.

Nothing for you to see here. Please move along.

[BlackCobra43]

What if I have a really, really powerful microscope?

Matters of Size and Scope

[ackthpt]

the nanotransistors are just a few hundred millionths of a meter in size -roughly 100 times smaller than the components used in today's microprocessors.

We're going to have a devil of a time soldering these things, not to mention fitting them with heatsinks...

Bandaru says the main remaining worry is how to manufacture complex nanotube-based circuitry reliably. Nonetheless, he is optimistic about the future of nanotube-based electronics.

"One must remember that for the Pentium chips which now have over 500 million transistors, the progenitor was a simple integrated circuit with two transistors in 1958," Bandaru says. "We are probably at the same stage with Y-junctions and the future looks good."

37 years? I can't wait that long! Where's the Fast Forward on these things?

Coming Soon: Time Travel

[DaSpudMan]

Looks like a Flux Capacitor to me.

Old News

[TripMaster Monkey]

This paper suggests that this sort of thing was being done 5 years ago.

From the paper:

Also, Papadopoulos et al introduced a Y-junction formation technique using branched nanochannel alumina templates (Papadopoulos, 2000).

Math

[Anonymous Coward]

[B]ut the nanotransistors are just a few hundred millionths of a meter in size -roughly 100 times smaller than the components used in today's microprocessors

So, uh, they are a few hundred millionths of a meter in size -- or to put it in clearer terms, a few tens of nanometers in size. That'd put them in the 30-60nm range. Intel's currently making chips on a 90nm process, and intends to start making them on a 65nm process by the end of the year.

That's not a 1/100x size improvement

Re:size vs heat in 50 years

[ajs318]

What you have to remember about heat is that electronics only get hot because they are never perfect conductors nor perfect insulators {though we can make nearer-perfect insulators than we can conductors}. A perfect conductor will never get hot, no matter how much current you put through it, because the voltage drop across it will be nil and power = voltage * current. Nor will a perfect insulator, because this time, the current through it will be nil.

CMOS is based around two transistors, a P-channel FET which goes conductive when the gate is driven low, and an N-channel FET which goes conductive when the gate is driven high. The P-FET is trying to pull the output high and the N-FET is trying to pull it low. Both the gates are joined together, and this is the input. This is a simple NOT gate.

For a NAND gate, where any input 0 will drive the output to a 1, we have several P-FETs in parallel trying to drive the output high, and so many N-FETs in series trying to drive the output low. Each P-FET gate joined to an N-FET gate is one input. When they are all high, all the N-FETs turn on allowing the output to go low; when any one is low, the chain of N-FETs is broken, one or more P-FETs turn on, and the output goes high. For a NOR gate, where any input 1 will drive the output to a 0, we put the Ns in parallel and the Ps in series. You can make AND gates from NAND+NOT, OR gates from NOR+NOT, and any other combination you like. In fact you really don't need both NAND and NOR, because you can make either one out of the other; but it turns out they're equally as easy to make as each other in CMOS {not like many other technologies}.

In an ideal world this would never dissipate any power, since the input cannot be high and low at the same time so only one of the transistors will ever be on. In practice what happens is that the gates act like capacitors which take a finite time to charge and discharge. They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little. It's not a dead short circuit of course, otherwise something would give way ..... hopefully a fuse.

Now every time something changes state, you get a little pulse of heat. Which is why fast processors need cooling. Additionally, to make sure that the logic gate output has changed state before the next clock pulse, you need to make the gate capacitances charge up quickly -- which means using a higher voltage than you could get away with at lower speeds. But 2x more volts means 2x more amps means 4x more watts.

Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.

Re:100nm?

[sleepingsquirrel]

Am I missing something here?

Yes. The 65nm refers to the transistors gate length, which is only a small portion of the transistor. See some transistor cross-sections. Look at the first diagram, look at the red colored rectangle above and between the two blue regions labeled "S" and "D" (for "Source" and "Drain"). That red part is the gate.

Let's Get Small Again

[Doc Ruby]

"the progenitor was a simple integrated circuit with two transistors in 1958 ... [w]e are probably at the same stage with Y-junctions"

Intel debuted the 4004, the first commodity microprocessor chip, in 1971 with 2300 transistors. That's 13 years, during which we had a space race (and Minuteman missile program) to stimulate investment. Today we have $trillions in returns on chip investment as stimulus, as well as an existing investment/manufacturing/marketing infrastructure. As well as highly useful micron-scale chips and software for design. So perhaps we're looking at a breakthrough "nanoprocessor" sometime earlier than 2028.

Meanwhile

[Julian Morrison]

Senior figures in the Bush administration were in talks with scientists, to see if a way could be found to fit these "naked" transistors with trousers.