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Intel Reveals Next-Gen CPUs
EconolineCrush writes "Intel has revealed its next generation CPU architecture at the Intel Developer Forum. The new architecture will be shared by 'Conroe' desktop, 'Merom' mobile, and 'Woodcrest' server processors, all of which were demoed by Intel CEO Paul Otellini. Rather than chasing clock speeds, Intel is focusing on lowering power consumption with its new architecture. Otellini claimed that Conroe will offer five times the performance per watt of the company's current desktop chips. He also ran the entire keynote presentation on a Merom laptop, and demoed Conroe on a system running Linux."
http://www.anandtech.com/printarticle.aspx?i=2504X JsX3Jldmlld19JRD0xNTAy. php?dXJsX3Jldmlld19JRD0xNTA0. php?dXJsX3Jldmlld19JRD0xNTAz1 23.html
http://theinquirer.net/?article=25623
http://www.hexus.net/content/reviews/review.php?d
http://www.hexus.net/content/reviews/review_print
http://www.hexus.net/content/reviews/review_print
http://www.tomshardware.com/hardnews/20050823_133
TR also has additional details on the architecture itself.
Because batteries are more mature than electronics.
Honestly there just is not that much room for improvement unless someone makes a huge break through.
If you think about the requirements for a battery they are pretty harsh.
1. Relatively none toxic
2. Relatively none explosive,
3. Last a long time.
4. Cheap.
See my blog http://ilovecookes.blogspot.com/ for light hearted technical information.
Instead of Anand's pictures of PowerPoint slides, here's some actual info from TechReport:
"IDF -- On the heels of Intel's announcement of a single, common CPU architecture intended to drive its mobile, desktop, and server platforms, the company has divulged additional details of that microarchitecture. This dual-core CPU design will, as we've reported, support an array of Intel technologies, including 64-bit EM64T compatibility, virtualization, enhanced security, and active management capabilities. Intel says the new chips will deliver big improvements in performance per watt, especially compared to its Netburst-based offerings.
At 14 stages, the main pipeline will be a little bit longer than current Pentium M processors. The cores will be a wider, more parallel design capable of issuing, executing, and retiring four instructions at once. (Current x86 processors are generally three-issue.) The CPU will, of course, feature out-of-order instruction execution and will also have deeper buffers than current Intel processors. These design changes should give the new architecture significantly more performance per clock, and somewhat consequently, higher performance per watt.
Unlike Intel's current dual-core CPU designs, which don't really share resources or communicate with one another except over the front-side bus, this new design looks to be a much more intentionally multicore design. The on-die L2 cache will be shared between the two cores, and Intel says the relative bandwidth per core will be higher than its current chips. L2 cache size is widely scalable to different sizes for different products. The L1 caches will remain separate and tied to a specific core, but the CPU will be able to transfer data directly from one core's L1 cache to another. Naturally, these CPUs will thus have two cores on a single die.
The first implementation of the architecture will not include Hyper-Threading, but Intel (somewhat cryptically) says to expect additional threads over time. I don't believe that means HT capability will be built into silicon but not initially made active, because Intel expressly cited transistor budget as a reason for excluding HT.
On the memory front, the new architecture is slated to have the ever-present "improved pre-fetch" of data into cache, and it will also include what Intel calls "memory disambiguation." That sounds an awful lot like a NUMA arrangement similar to what's found on AMD's Opteron, but I don't believe it is. This feature seems to be related to a speculative load capability instead..
The server version of the new Intel architecture, code-named Woodcrest, will feature two cores. Intel is also talking about Whitefield, which has as much as twice the L2 cache of Woodcrest and four execution cores.
The company has decided against assigning a codename to this new, common processor microarchitecture, curiously enough. As we've noted, the first CPUs based on this design will be available in the second half of 2006 and built using Intel's 65nm fabrication process. "
Kaa
Kaa's Law: In any sufficiently large group of people most are idiots.
Nope: current Intel CPU is 100+ Watts, a hard drive is like 15 Watts.
... it clearly states that it combines the 64bit and netburst from the P4. M$ already told intel to fcuk off when it came to itanium 64bit. Hence EM64T that they have now which is compatible with AMD's implementation.
"combining the lessons learned from the Pentium 4's NetBurst and Pentium M's Banias architectures. To put it bluntly, the next-generation microprocessor architecture borrows the FSB and 64-bit capabilities of NetBurst and combines it with the power saving features of the Pentium M platform."
For example it has been long known that you can have very long lasting nuclear batteries using betavoltaics (couple of a source of beta radiation and a p-n junction and you have your battery), but would you put it on your lap that is the question.
Either it has so much shielding that it is too heavy, or it is nice and light and will make you grow another set of legs (or something else down there...).
But I remember that there was an article about someone developing such a battery here the link, I think.
Intel plans to release these in Q2 2006. They will use a 65nm process, support dual cores, and get 5x the per-watt performance of the Prescott EE.
AMD has dual core chips available now, that get 3-5x the per-watt performance of Intel's Prescott EE line (depending on how they define certain things - Idle? Mean power/load? Peak realistic-but-not-theoretical? TDP?).
And AMD only uses 90nm at the moment, and will have two 65nm fabs up by the end of this year - Which will give them another nice boost in terms of per-watt performance.
I love the idea of a truly "new" CPU line entering the arena, but this smells an awfully lot like more of Intel playing catch-up, and in a way they won't win.
Unless the Pentium-M line has, for whatever reason, reached a hard wall for performance, Intel would have done better to expand it to multi core - Perhaps jump right to 4 cores just to bypass the whole "catch up with dual" criticism - And dropped the price to undercut AMD (at least per-core). But this? Well, it has potential, but unless Intel has decided to seriously under hype a major announcement, I won't lose any sleep worrying that I just upgraded three machines to readiness for AMD's X2 line (can't afford the damn things yet, so currently just running Winchester 3000s, but all just a chip-swap away from going to X2).
Lake Conroe, Oregon...Intel's largest campus is in Oregon.
...I'm a bit confused about woodcrest, though...
Merom, Israel...Intel does much R&D work is Israel.
-ds
where/what was the inspiration for Woodcrest?
A new upscale housing community starting is the low 300's. You'll find one in pretty much every suburban area in North America, and they're all exactly the same.
Sorry, but this argument doesn't hold a lot of water. Fat, for instance, has an energy density of 38 kilojoules per gram, whereas lithium-ion has a density of 0.72 kilojoules per gram. Fat, while flammable, is far less dangerous than lithium-ion.
Lots of materials have a high energy density and are still very safe and stable. The problem, of course, is that extracting electrical energy from them is not incredibly easy to do. However, we should not say that high energy density is inherently unsafe.
I have seen the future, and it is inconvenient.
Intel's original idea was to find a way to more aggressively pipeline their CPU design, allowing for higher clock rates. Increasing the number of pipeline stages allows you to reduce the number of transistors between stages, reducing propagation delay and increasing maximum clock rate.
In a vaccuum, this makes sense. If the instruction reorderer and/or compiler are smart enough, you can keep that pipeline full and take advantage of that higher clock rate. Indeed, there have been examples of carefully-crafted code that ran very well on this architecture.
Unfortunately, real software is quite different from the ideal sort of thing that runs well on the P4. Too many hazzards (branches and instruction dependencies) limited how full you could keep the pipeline. The CPU would execute instructions out of order, but there's only so smart you can make it. And not all branch hazzards can be fixed by a branch predictor.
Intel's hyperpipelined design was a relative failure. Sure, they could clock it 50% faster than an AMD, but that's what it took to make up for the increased pipeline stalls. Performance-wise, it was a wash. In other respects, it was a loss, because the processors required more power, more expensive cooling, and more expensive fabrication.
After a while, Intel came up with a way to make use of that wasted bandwidth. Why not fill those pipeline bubbles with another, independent execution stream? HyperThreading was born. Not altogether a bad idea. In many cases, it allowed up to 30% better over-all performance for multi-threaded apps, and giving you another CPU core (virtual or not) is always a good way to reduce latency.
In a last-ditch attempt to try to break the MHz barrier, Intel came out with the Northwood core. They lengthened the pipeline from an excessive 20 stages to an absurd 31 stages (not including the x86-to-RISC translator before the trace cache). To make up for the additional hazzards, Intel had to develop even more aggressive branch prediction and use larger reorder buffers. Unfortunately, this too turned out to be a performance wash, with an associated increase in power requirements.
At the same time, notebook computers started to overtake desktops in popularity. Low-power became MUCH more important than high-performance. The P4 really could not compete in this space, so Intel hired an Israeli team to develop a whole new architecture. To make a long story short, they basically reverted back to the P3 architecture (a relatively short pipeline), but added on all of the P4's advancements in reordering an branch prediction.
Think about that. Intel had made some mistakes, but they were GOOD mistakes. In order to work around the deficiencies in their P4 design, they had to develop some very impressive and advanced ways of keeping that pipeline full. Of course, any pipeline is going to have hazzards, so imagine applying that technology to a much shorter pipeline. The result was impressive. While the slower clock speed of Banias/Centrino was noticable under SOME circumstances (as it is with AMD processors), the majority of the time, the performance was excellent, even at a lower clock rate and lower power requirement.
The development of the P4 was a technical failure, but it was also a valuable phase in Intel's life. These lessons learned are going to be the basis for Intel's future success in efficient CPUs. Finally, I think Intel will be able to compete with AMD, even WITHOUT dubious deals with resellers designed to lock AMD out of the market.
For example it has been long known that you can have very long lasting nuclear batteries using betavoltaics (couple of a source of beta radiation and a p-n junction and you have your battery), but would you put it on your lap that is the question.
Considering that plutonium beta cell batteries were used in pacemakers, I wouldn't be too worried about that. I think the shielding could be lightweight enough.
But getting rid of used batteries could be a real problem.