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Intel Reveals Next-Gen CPUs
EconolineCrush writes "Intel has revealed its next generation CPU architecture at the Intel Developer Forum. The new architecture will be shared by 'Conroe' desktop, 'Merom' mobile, and 'Woodcrest' server processors, all of which were demoed by Intel CEO Paul Otellini. Rather than chasing clock speeds, Intel is focusing on lowering power consumption with its new architecture. Otellini claimed that Conroe will offer five times the performance per watt of the company's current desktop chips. He also ran the entire keynote presentation on a Merom laptop, and demoed Conroe on a system running Linux."
With Laptop sales "Surging" and technology growing exponentially, isn't it time to look at the batteries? You hear a lot about faster video cards/ CPUs and memory, but almost nothing about Next-Gen batteries. Battery technology hasn't really evolved at the same rate as other computer components, has it? I personally feel the bottleneck resides in the batteries and for the industry to progress (on a whole), they're going to have to take a look at all aspects.
"Simplify, simplify, simplify!" Thoreau
Rather than chasing clock speeds, Intel is focusing on lowering power consumption with its new architecture.
Exactly what we've all been waiting for. Is Intel Good(tm) now?
The Digital Couture Collection
Awesome. Now I'll be able to run 4 times as many CPUs with my 1000w PSU.
Ok, Conroe appears to be a lake in Texas, Merom is a bluff near the Wabash river in Indiana...where/what was the inspiration for Woodcrest?
So instead of clock speed how about execution speed of standard benchmarks on a reference machine? Or would that show how much they suck per dollar next to AMD?
http://www.anandtech.com/printarticle.aspx?i=2504X JsX3Jldmlld19JRD0xNTAy. php?dXJsX3Jldmlld19JRD0xNTA0. php?dXJsX3Jldmlld19JRD0xNTAz1 23.html
http://theinquirer.net/?article=25623
http://www.hexus.net/content/reviews/review.php?d
http://www.hexus.net/content/reviews/review_print
http://www.hexus.net/content/reviews/review_print
http://www.tomshardware.com/hardnews/20050823_133
TR also has additional details on the architecture itself.
We now have batteries powered by urine!
Who hasn't wanted to pee on their new laptop? Marks your territory and provides hours of power!
what else could you want?
Starsucks
Does anybody know what instruction set these three new processors implement? The article states that these are 64-bit CPUs, but doesn't say whether they feature the AMD64 or the Itanium instruction set.
John Sauter (J_Sauter@Empire.Net)
Fundamentally, most markets of any age undergo specialization, niches form, and those most fitted to the niches, do best. But having a unified architecture between server / laptop / desktop flies in the face of that; it either claims there is no niche market anywhere, or that there is a "killer chip" which fits all niches better than anything else.
Now, I can guess what Intel would choose of those options, but is there something about the chip industry that makes it immune to this specialization idea? What am I missing?
In Soviet Russia, us are belong to all your base.
The screenshots make it look like Intel isn't including HT with this next gen core. Is that because it's likely the pipeline is shorter? I thought it would be uber-cool to have a dual-core CPU with HT for some awesome synthetic 4-core action. But, I guess the real question is: Should I care about HT anymore?
It's been YEARS since Transmeta began preaching performance/watt, and it looks like right now, when Transmeta has some big contracts (with Sony, Microsoft, Fujitsu, etc) beginning to pay off, Intel finally figures it out.
Of course, Transmeta's already GOT the technology to cut leakage by tremendous amounts... Given that they are no longer a direct competitor of Intel's, it would make some sense if Intel simply licensed Transmeta's LongRun2 tech. But what do I know? I'm always foolishly choosing the better technology instead of the better marketing.
It was a joke! When you give me that look it was a joke.
So much for Moore's Law. So much for the supposedly inexorable march of technology. So much for that nonsense about increasing CPU performance, you all didn't really want 4 GHz anyway, did you?
People have been predicting the demise of Moore's Law for years. It's funny that it's happened and nobody seems to notice.
While I admit there's been times I WANTED to get back at my laptop for being so slow, the smell factor stopped me. Okay that and the cost, not to mention that I could get zapped in a very private place!
Urea don't small like roses, just sniff my cat box after the cat's used it. Yurk! (Actually, just be in the room after he goes. Bleah!)
MSBPodcast.com The opinions expressed here are my own. If you don't like 'em... Think up your own stuff.
I am glad to see that Intel is addressing power consumption with the server chip Woodcrest. After all, desktops and laptops are small potatoes compared to servers when it comes to power usage. For corporations with large server implementations, I could see this saving a lot of power (=$). Good move for Intel; lower power bills are good leverage for new technology purchases -- many of us used that same argument to upgrade from CRTs to LCDs. It is nice to finally have something to be excited about from Intel again.
This is something Intel needs to do to stay in the CPU market. Their NetBurst architecture has allowed AMD to capture the hearts of the enthusiests as it is a better processor. (Note: the mass market has many other factors besides which processor is best in determining sales.)
While I currently favor AMD's processors, The Pentium M is a magnificant piece of hardware. With Intel basing their future processors on the Pentium M they are going to give AMD a run for their money. This will force AMD to drop their prices to a more reasonable level.
The one thing Intel is doing that IMHO is wrong is changing the definition of performance from clock speed to performance/watt. This tells us nothing of the performance of the processor or the power required to run it. Instead we should have two basic measurements for all processors: performace and power consumption. Most people are able to do simple calculations such as division on their own or with a calculator. The is no need to hide the actual performance from the end users.
Instead of Anand's pictures of PowerPoint slides, here's some actual info from TechReport:
"IDF -- On the heels of Intel's announcement of a single, common CPU architecture intended to drive its mobile, desktop, and server platforms, the company has divulged additional details of that microarchitecture. This dual-core CPU design will, as we've reported, support an array of Intel technologies, including 64-bit EM64T compatibility, virtualization, enhanced security, and active management capabilities. Intel says the new chips will deliver big improvements in performance per watt, especially compared to its Netburst-based offerings.
At 14 stages, the main pipeline will be a little bit longer than current Pentium M processors. The cores will be a wider, more parallel design capable of issuing, executing, and retiring four instructions at once. (Current x86 processors are generally three-issue.) The CPU will, of course, feature out-of-order instruction execution and will also have deeper buffers than current Intel processors. These design changes should give the new architecture significantly more performance per clock, and somewhat consequently, higher performance per watt.
Unlike Intel's current dual-core CPU designs, which don't really share resources or communicate with one another except over the front-side bus, this new design looks to be a much more intentionally multicore design. The on-die L2 cache will be shared between the two cores, and Intel says the relative bandwidth per core will be higher than its current chips. L2 cache size is widely scalable to different sizes for different products. The L1 caches will remain separate and tied to a specific core, but the CPU will be able to transfer data directly from one core's L1 cache to another. Naturally, these CPUs will thus have two cores on a single die.
The first implementation of the architecture will not include Hyper-Threading, but Intel (somewhat cryptically) says to expect additional threads over time. I don't believe that means HT capability will be built into silicon but not initially made active, because Intel expressly cited transistor budget as a reason for excluding HT.
On the memory front, the new architecture is slated to have the ever-present "improved pre-fetch" of data into cache, and it will also include what Intel calls "memory disambiguation." That sounds an awful lot like a NUMA arrangement similar to what's found on AMD's Opteron, but I don't believe it is. This feature seems to be related to a speculative load capability instead..
The server version of the new Intel architecture, code-named Woodcrest, will feature two cores. Intel is also talking about Whitefield, which has as much as twice the L2 cache of Woodcrest and four execution cores.
The company has decided against assigning a codename to this new, common processor microarchitecture, curiously enough. As we've noted, the first CPUs based on this design will be available in the second half of 2006 and built using Intel's 65nm fabrication process. "
Kaa
Kaa's Law: In any sufficiently large group of people most are idiots.
The problem is that the physics for how to increase the number of transistors on a chunk of silicon is very well understood and the physics of how to make better batteries is not.
To double the number of transistors on a processor is primarily a matter of lithography, that is etchich smaller and smaller lines into an existing wafer. Same materials, more or less, and same technique, more or less. With batteries, it's far more hit and miss.
The technology and fabrication process to make a lead-acid battery is vastly different than NiCd. NiMh is somewhat similar to NiCd, but then Lithium Ion is rather different and requires a lot more technology to make it work. Then you've got fuel cells as a possibility, and that's vastly different from anything I just described.
There's a lot of effort being put into battery research because everybody understands what a fundamental limitiation it is to everybody's dreams of pervasive wireless. It's rather ironic to describe these internet coffee shops as having "wireless" when you still have to have A/C power to do anything. The problem is that it does not have the clear and obvious path that CPU's have had.
I expect that fuel cells will eventually be the way to go. Still there's a certain inconvenience in them. If I want to charge my laptop batteries, i just plug in my laptop. If I've got a fuel cell, do I have to buy numerous cells? Do I have to fill them up with methanol, etc? It doesn't seem like there's a panacea for portable power (and other p words) anytime soon.
This sig has been temporarily disconnected or is no longer in service
I have to wonder if Intel basically ditching the last 5 years of CPU development in favor of their Israeli skunkworks ranks at or above the famous Microsoft IE U-turn?
I mean, Intel sold millions and spent billions on Netbu(r|)st, and hit the wall far before the 5+ghz figures bandied about back in the day. This is basically ctrl-alt-del on a large part of their roadmap, though I'm sure they'll still be selling 'traditional' P4s for awhile.
Intel plans to release these in Q2 2006. They will use a 65nm process, support dual cores, and get 5x the per-watt performance of the Prescott EE.
AMD has dual core chips available now, that get 3-5x the per-watt performance of Intel's Prescott EE line (depending on how they define certain things - Idle? Mean power/load? Peak realistic-but-not-theoretical? TDP?).
And AMD only uses 90nm at the moment, and will have two 65nm fabs up by the end of this year - Which will give them another nice boost in terms of per-watt performance.
I love the idea of a truly "new" CPU line entering the arena, but this smells an awfully lot like more of Intel playing catch-up, and in a way they won't win.
Unless the Pentium-M line has, for whatever reason, reached a hard wall for performance, Intel would have done better to expand it to multi core - Perhaps jump right to 4 cores just to bypass the whole "catch up with dual" criticism - And dropped the price to undercut AMD (at least per-core). But this? Well, it has potential, but unless Intel has decided to seriously under hype a major announcement, I won't lose any sleep worrying that I just upgraded three machines to readiness for AMD's X2 line (can't afford the damn things yet, so currently just running Winchester 3000s, but all just a chip-swap away from going to X2).
Hmmm.... did you notice in the slides it was all integer performance/watt? They never told us actual absolute performance, and never floating-point performance. My inner geek tells me there is much hype and little solid evidence of anything.
You forgot to mention:
Anyone who says they will be modded as a Troll will be modded +5
While it's not a perfect metric, it is very useful for some very important target markets. Some companies crunch numbers continuously for profit. They have datacenters filled with thousands upon thousands of Opterons or Xeons or what-have-you. The battles they are fighting (in terms of maximizing their profits) are all about power/heat density (how many GFlops can I cram into X square feet of datacenter space and still be able to supply the proper power and cooling), and performance per watt (for every $100,000 I spend on electric bills running this datacenter, how many calculations can I complete?).
11*43+456^2
Finally! We move on from x86. We have advanced beyond 20 year old technology.
That's a bit like saying, "Finally! We move on from English. We have advanced beyond centruries old technology."
The X86 is just a language. No recent processor actually uses it raw. There may be some inefficiencies in the language itself, but the most significant have been reduced by extensions and smart compilers which avoid those constructs. The remaining inefficiencies are worth the backwards compatability, but they are minimal anyway.
A lot of people keep complaining about this "ancient" instruction set, but the reality is that it doesn't matter at this point. Even low-level drivers are being written in C due to fast processors and infinite storage space.
Yeah, sure, it would be nice to move to another instruction set, but previous efforts have failed. Intel's 64 bit chip requires a monstrously complex compiler, but it's wicked fast/efficient. But the P4 has surpassed it with it's "inefficient, outdated, and clunky" instruction set.
There's so much momentum on the X86 caravan that to develop something else and surpass the caravan is a hurculean task. Currently it is more effective to improve the architecture that runs X86 than it is to make a new instruction set and try to improve the architecture at the same time. (which is required since just changing the instruction set won't advance the performance enough to compete with the X86 that comes out when you're ready to release)
-Adam
Yeah! Go AMD! Surely the, as a member of the Trusted Computing Platform Alliance (TCPA) won't implement hardware DRM. It's just Intel who, as a member of the Trusted Computing Platform Alliance implemented the TCPA specification. And Apple clearly moved to Intel just to get access to this, because we know that IBM, as a member of the Trusted Computing Platform Alliance, would never have implemented it in their chips.
I am TheRaven on Soylent News
Intel's original idea was to find a way to more aggressively pipeline their CPU design, allowing for higher clock rates. Increasing the number of pipeline stages allows you to reduce the number of transistors between stages, reducing propagation delay and increasing maximum clock rate.
In a vaccuum, this makes sense. If the instruction reorderer and/or compiler are smart enough, you can keep that pipeline full and take advantage of that higher clock rate. Indeed, there have been examples of carefully-crafted code that ran very well on this architecture.
Unfortunately, real software is quite different from the ideal sort of thing that runs well on the P4. Too many hazzards (branches and instruction dependencies) limited how full you could keep the pipeline. The CPU would execute instructions out of order, but there's only so smart you can make it. And not all branch hazzards can be fixed by a branch predictor.
Intel's hyperpipelined design was a relative failure. Sure, they could clock it 50% faster than an AMD, but that's what it took to make up for the increased pipeline stalls. Performance-wise, it was a wash. In other respects, it was a loss, because the processors required more power, more expensive cooling, and more expensive fabrication.
After a while, Intel came up with a way to make use of that wasted bandwidth. Why not fill those pipeline bubbles with another, independent execution stream? HyperThreading was born. Not altogether a bad idea. In many cases, it allowed up to 30% better over-all performance for multi-threaded apps, and giving you another CPU core (virtual or not) is always a good way to reduce latency.
In a last-ditch attempt to try to break the MHz barrier, Intel came out with the Northwood core. They lengthened the pipeline from an excessive 20 stages to an absurd 31 stages (not including the x86-to-RISC translator before the trace cache). To make up for the additional hazzards, Intel had to develop even more aggressive branch prediction and use larger reorder buffers. Unfortunately, this too turned out to be a performance wash, with an associated increase in power requirements.
At the same time, notebook computers started to overtake desktops in popularity. Low-power became MUCH more important than high-performance. The P4 really could not compete in this space, so Intel hired an Israeli team to develop a whole new architecture. To make a long story short, they basically reverted back to the P3 architecture (a relatively short pipeline), but added on all of the P4's advancements in reordering an branch prediction.
Think about that. Intel had made some mistakes, but they were GOOD mistakes. In order to work around the deficiencies in their P4 design, they had to develop some very impressive and advanced ways of keeping that pipeline full. Of course, any pipeline is going to have hazzards, so imagine applying that technology to a much shorter pipeline. The result was impressive. While the slower clock speed of Banias/Centrino was noticable under SOME circumstances (as it is with AMD processors), the majority of the time, the performance was excellent, even at a lower clock rate and lower power requirement.
The development of the P4 was a technical failure, but it was also a valuable phase in Intel's life. These lessons learned are going to be the basis for Intel's future success in efficient CPUs. Finally, I think Intel will be able to compete with AMD, even WITHOUT dubious deals with resellers designed to lock AMD out of the market.
For example it has been long known that you can have very long lasting nuclear batteries using betavoltaics (couple of a source of beta radiation and a p-n junction and you have your battery), but would you put it on your lap that is the question.
Considering that plutonium beta cell batteries were used in pacemakers, I wouldn't be too worried about that. I think the shielding could be lightweight enough.
But getting rid of used batteries could be a real problem.