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Next Generation Chip Research

Posted by ScuttleMonkey on from the bet-you-can't-eat-just-one dept.

Nyxs writes to tell us Sci-Tech-Today is reporting that researchers at the University of Texas are taking a new approach to designing microprocessor architecture. Doug Berger, a computer science professor at the University of Texas, and his colleagues hope to solve many of the pressing problems facing chip designers today with the new "microprocessor and instruction set architecture called Trips, or the Teraop Reliable Intelligently Adaptive Processing System."

3 of 174 comments (clear)

  1. But... by ankarbass · · Score: 0, Redundant

    Is it reliable?

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  2. Re:They have CS Programs in Texas? by putko · · Score: 0, Redundant

    Don't look down on the Texans. It has one of the highest ranked computer engineer programs in the country. I've heard of Doug Berger before and we have read his research papers and use his simulators (made between him and Todd Austin of Wisconsin) in our graduate classes at CMU (I'm BS&MS ECE, CS '01).

    I didn't ask about how well their program is rated. Has UT produced any programs that people use? E.g.

    MIT -- Kerberos
    Berkeley - RISC, BSD Unix, RAID, TCP/IP networking as standard OS feature
    Stanford -- RISC
    Cornell -- Ensemble, Horus, Spinglass -- distributed programming toolkits
    Caltech -- Carver Mead (VLSI method, VLSI tools, machine vision)


    UT -- a simulator that you've used. What sort of simulator, please?

    E.g. Berkeley developed SPICE, a tool used to simulate circuits. Last I heard, it was the standard tool to use for that stuff. Here's the project page: http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE /

    Austin also has a high number of tech companies around - heck, AMD, IBM, Intel, Freescale, just to name a few.

    I didn't ask what firms work there. I want to know what software people at UT have made that is worth talking about.

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  3. Old technology on hyperdrive by dascandy · · Score: 0, Redundant

    Is it just me or does the article explain '95 technology?

    It tells about loading blocks of instructions at a time (say, a cache line), then executing them whenever the data is available (which is called out-of-order execution).

    In other words, they're going to overclock a pentium-I to 10ghz and add an excess in pipelines to make it reach a teraflop. I could've done that (given the p1 design).