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Sun Open-Sourcing UltraSPARC Design
AKAImBatman writes "While everyone was busy with the holiday season, Sun Microsystems quietly announced the start of the OpenSPARC project. Unlike previous CPUs that were based on the "Open" SPARC specifications (such as LEON), Sun is releasing the complete Verilog source code to their latest and greatest microprocessor. Their current time frame for releasing the source code to the public is in March of 2006. Given their success with the OpenSolaris project, it seems that this is likely to be more than just vaporware. So get out your Virtex FPGAs and your Verilog compilers, and let's get ready to hack some hardware!"
I'm all for their ideas on OpenSolaris, but this may be going a bit too far. Didn't they open Solaris to sell more hardware? I'm pretty sure a company that doesn't make money is like a species that doesnt reproduce... dead.
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So get out your Virtex FPGAs and your Verilog compilers, and let's get ready to hack some hardware!"
:)
Thats going to give us a nice biiig processor
These new servers absolutely rock, and at superb prices.
I once had the pleasure of a 4-way Opteron v40z with a development version of 64-bit Solaris 10. It was a screamer, especially compared to our 4-way Dell P4 Xeon box, and 64-bit.
It was plenty fast enough to host 4 zones and several developers working on KDE, gcc and all manner of other stuff.
At last, Sun looks like it's turning the corner (despite the best efforts of some of its PHBs - no names mentioned).
Good luck Sun.
There are some questions. FPGAs aren't that big... a XC2V6000 that costs $4500 is about the right size for four cores of a simple 4-SIMD 24bit fixed-point signal processor - a UltraSPARC will not fit in it, unless it's seriously cut down.
Also speed of FPGAs is a huge let-down, unless a design takes advantage of their structure. There is no reason to believe that the processor will be designed for FPGAs... It is likely to be therefore very slow, even if you can implement it.
FP! SP! TP!
Frame Pointer
Stack Pointer
ummmm...
What's TP??
Oh yeah
Toilet Paper - aka SCO Legal Documentation.
open source or not, these coolthreads processors are the first thing from Sun that looks exciting in the last six years. Finally, some leadership. Too late?
Rat brains are cheaper and self-replicating.
Go to http://www.opencores.org/ for more examples of Open Hardware.
Jonathan Schwartz's Weblog: Our Most Valuable Intellectual Property
And now you have a pretty good idea of what's in store for tomorrow. (Pay careful attention to the "open market for parts" comment - we're planning on delivering an extraordinary surprise to the industry. No sense in letting the software folks have all the fun...)
You can license ARM and PowerPC cores -- but they will probably get a bit cheaper if this one is available for free.
f pgas/virtex/virtex_ii_pro_fpgas/capabilities/power pc.htm
Right now Xilinx and Altera make user-configurable FPGA processors. Most of the processor is fixed, but you can encode what happens for special instructions. Here's one: http://www.xilinx.com/products/silicon_solutions/
Now if Sun is giving away the processor, there's no reason for you to pay more for a PowerPC-based design -- someone will make a "cheapo" FPGA-extendable UltraSPARC.
http://www.thebricktestament.com/the_law/when_to_
So, how long until we can buy discount chinese-made ultraSPARC chips at Wal-Mart?
It's a little bit early to say yet, but if all the "design source, verification suite and simulation models" are released as open-source (as TFA said), and if the license would allow design and manufacture of systems based on that chip without paying an arm and a leg (which TFA didn't mention), I'd say: "Woohooo!", and I'd say this for all the developing countries, including China, India, etc.
And I hope this will "sparc" a revival of the sparc acrhictecture!
HP should've done the same with the Alpha architecture instead of letting it die a forgotten death. What a shame!
Excluding the fab, it takes an enormous amount of design and layout effort to go from RTL to masks. SparcT1 is not a purely synthesized design. Even if it were, the tuning required to make synth work is a nontrivial effort requiring a significant tool foundry.
I suppose that once we have open source versions of: schematic capture, synthesis, floorplanning, layout, timing, validation, and mask generation, then we can focus on an open source process and an open source fab. Not bloody likely!!!
I think the biggest benefit here is that now both hackers and Universities now have a REAL architecture to study in their classrooms. I'll definitely be on the prowl for resumes of students who studied real microprocessor Verilog in college, and not simple ISCAS circuits or architectures from the 1980's.
https://www.accountkiller.com/removal-requested
It's the difference between an open spec and open source. Nobody seems to understand that any more.
Pardon my threadjack, but I just realized that the editors secretly switched my link for a competing brand. Unlike Folgers, I'm afraid it's much cooler to get processor news straight from the horse's mouth.
Javascript + Nintendo DSi = DSiCade
Someone there must have been paying attention to the Open Graphics Project. They're working on a design for an open source graphics card. Naturally, the drivers will be open source, but ultimately, so will the Verilog code to the internal GPU design.
Sun's microSPARC processor has been available for download for quite some time. It is available as synthesizable verilog source code and I think it comes with a PCI master. If sparc is not your style, download their picoJava processor instead.
Perhaps you should start comparing prices, then:
So, it would appear that Sun's support prices are actually lower rather than beating Red Hat's. In fact, for one of Sun's cheapest server systems, you can get Platinum support for $2304 for three years. Platinum support includes both 24/7 software support and 24/7 two-hour response time on-site hardware support. That's cheaper then one year of Red Hat's software-only 24/7 support.
Again, compare prices:
So, the Sun server may not be as cheap as building a system out of spare parts lying around in your basement, but it really is pretty cheap compared to the competition in that space.
Try fitting a P4 or UltraSPARC in a Virtex4-1xxLX, you are going to run into several problems.
1) The ASIC runs at 1GHz+ frequency, the V4 implementation would run around 300MHz at best and cost over $10k for the FPGA alone.
2) Most FPGAs block-RAM and LUT-based RAM can be dual-ported at most, this is problematic for register files where a dozen registers may be concurrently accessed during any given cycle. This would require either register duplication or time-multiplexed register access and a corresponding down-clocking of everything else.
3) Logic is expended pretty fast if you do stuff like 64x64 multipliers using logic only. Sure, there are dedicated multipliers in most modern low-cost FPGAs but these are hard-wired to handle DSP-centric MAC operations.
4) People are upset with desktop CPU's power usage but building similar CPUs on FPGAs would require many times more power to achieve the same performance since FPGA's switch fabric and general-purpose programmable elements have way more parasitic capacitance than ASICs' internal hard-wired traces and circuits. With ASIC, 1M logic gates is only ~6M transistors but a ~1M gate-equivalent FPGA with switch fabric and configuration bits goes beyond 50M transistors with much longer routing delays.
FPGAs are not particularly suitable for general-purpose processing where the system has extensive subsystem interdependencies and shared elements. Where they can truly shine is in applications where the data flow is mostly regular and where processing can be broken down into well-defined self-contained stages like telecom, crypto and DSP. Another area where FPGAs can shine is hard-realtime where they can have dedicated logic to handle time-critical events with 100% deterministic deadlines, unlike modern CPUs and OSes where realtime applications have to put up with unpredictable branch mispredicts, cache misses, preemption, out-of-order execution, etc.
That said, the UltraSPARC's verilog source should make for really interesting reading for logic and digital system engineers and academics like myself. This move makes a lot of sense: CPU designers need to hire new talent and this new talent needs to learn about common practice in real-world designs to be of any use or they'll spend most of their first months just catching up. With a real-world design in the wild, CPU-designer job postings could ask people to specify which architectural components they would like to improve and the interviews could steer towards presenting those improvements instead of often irrelevant technicalities.
Well it should be noted that the Dell server doesn't come with rails either, and they add $99 to the price of an entry level PowerEdge 850 for the "static" rails. These static rails are literally two pieces of metal as shown here, and don't telescope (much less have a cable management arm). If you want rails that actually let you pull the server all the way out of the rack - still no cable management - well, those are $129. It's pretty sad how much any vendor will gouge you on rails. These rail prices from Dell are actually much lower than in the past as well. A few months ago rails for a few PowerEdge 750s I ordered were priced at $200 per server. To their credit, Sun seems to have their 2U server rails priced the same as their 1U offerings. Rails for a Dell 2850 are a painful $250.