Reduce Transistor Power Consumption

revelCyllufyalP writes to tell us that University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors. From the article: "In order to improve computer chips' performance, transistors' size and gate insulators have to be continuously shrunken so that more components can be packed into a single chip. Computer chip producers were hitting a wall in downscaling the transistors and gate insulators because of their inability to reduce the leakage current of the existing gate insulators. This new technique will help the chip producers to develop more powerful chips with low-power consumption."

Comments

Woohoo

[matr0x_x]

This may not sound like that big a deal, but let me assure you this is very significant to wireless infrastructure enhancement. One of the biggest limiting factors in wireless devices is power consumptions, so this is great news for the industry!

Re:Woohoo

[0racle]

How could this not sound significant to the general users of this site. The latest Athalons and Pentiums use how much power again? If these guys patent this idea, I'm guessing it could make them quite rich.

How do you reduce tunneling current?

[Beryllium Sphere(tm)]

The press release says they're getting several orders of magnitude less tunneling current through gate insulators. But tunneling happens because some portion of the electron's wavefunction extends to the other side of the insulator. Whst are they changing that would affect the physics? Or are they fixing a different kind of leakage and getting the press release wrong?

Re:How do you reduce tunneling current?

[soundsop]

It's easy to reduce the tunneling current through the gate. All you have to do is increase the thickness of the insulator. Unfortunately, this has the detrimental effect of reducing the effective capacitance of the gate, which in turn lowers the amount of current conducted by atransistor of a given size (lowering the current also lowers the speed). To make up for the lowered gate capacitance, researchers have been trying to increase the dielectric constant of the insulator. I'm guessing that they're proposing a method to increase the dielectric constant of the gate insulator. The devil is in the details of improving the dielectric constant without screwing up later processing steps or reducing the mechanical integrity of the wafer, etc.

Summary:

1. To lower gate leakage simply increase dielectric thickness.
2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
3. Profit.

Re:How do you reduce tunneling current?

[saifatlast]

I'm no expert, but even I can see that you missed a step here. Here, I'll fix it for you.

1. To lower gate leakage simply increase dielectric thickness.
2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
3. ????
4. Profit

Hope that clears things up for everyone.

Prior art?

[Dirtside]

University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors

Wayyyy ahead of you.

Where's the news?

[Anonymous Coward]

As probably one of the few semiconductor geeks on /., I have to say: Where's the news? Gate dielectrics are always made with rapid thermal processing on current technologies. Basically, stick a wafer in a chamber, flow some gas, turn on some super-high intensity
lamps, heat the wafer to >1000C for a very brief time, grow a few atomic layers of silicon dioxide (or some variant that includes nitrogen), turn off lamps, cool wafer, take it out of chamber.

From what little info is in the press release, it doesn't sound like they're doing anything revolutionary, so I'm curious why they claim they can reduce gate leakage by so much.

It is already done, old news

[karvind]

Gate oxides in current microprocessors are around 1.2-2 nm and are grown using RTP (rapid thermal process). A furnace oxidation is too fast. So yes industry already uses rapid thermal anneal (as suggested in TFA) for their gate oxides. Can anyone tell how is the new ?

Cuts 75% of power usage in current generation

[Markus Registrada]

In the latest generation of processors, 50% - 75% of the power consumption is this gate current leakage. In the next generation, it was looking to go over 90%.

What this really means is that the next generation has just become possible. As an incidental side benefit, current-generation laptops will be able to run cooler.

Re:Cuts 75% of power usage in current generation

[Markus Registrada]

Switching current runs only when a signal changes. Most signals don't change in most cycles, but the transistor gates leak continuously. Furthermore, as the transistors get smaller, the capacitance per transistor goes down, but the gate current leakage goes up inverse-exponentially -- or did. So, the switching current really goes up only linearly with the clock rate, but there was no upper limit for the leakage current.

Must be late...

[cagle_.25]

Heh...for just a second as my eyes hit the headline, I thought that the researchers had discovered some "direct tunneling" from Kentucky to the United Kingdom.

size vs heat

[esac17]

What you have to remember about heat is that electronics only get hot because they are never perfect conductors nor perfect insulators {though we can make nearer-perfect insulators than we can conductors}. A perfect conductor will never get hot, no matter how much current you put through it, because the voltage drop across it will be nil and power = voltage * current. Nor will a perfect insulator, because this time, the current through it will be nil.

CMOS is based around two transistors, a P-channel FET which goes conductive when the gate is driven low, and an N-channel FET which goes conductive when the gate is driven high. The P-FET is trying to pull the output high and the N-FET is trying to pull it low. Both the gates are joined together, and this is the input. This is a simple NOT gate.

For a NAND gate, where any input 0 will drive the output to a 1, we have several P-FETs in parallel trying to drive the output high, and so many N-FETs in series trying to drive the output low. Each P-FET gate joined to an N-FET gate is one input. When they are all high, all the N-FETs turn on allowing the output to go low; when any one is low, the chain of N-FETs is broken, one or more P-FETs turn on, and the output goes high. For a NOR gate, where any input 1 will drive the output to a 0, we put the Ns in parallel and the Ps in series. You can make AND gates from NAND+NOT, OR gates from NOR+NOT, and any other combination you like. In fact you really don't need both NAND and NOR, because you can make either one out of the other; but it turns out they're equally as easy to make as each other in CMOS {not like many other technologies}.

In an ideal world this would never dissipate any power, since the input cannot be high and low at the same time so only one of the transistors will ever be on. In practice what happens is that the gates act like capacitors which take a finite time to charge and discharge. They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little. It's not a dead short circuit of course, otherwise something would give way ..... hopefully a fuse.

Now every time something changes state, you get a little pulse of heat. Which is why fast processors need cooling. Additionally, to make sure that the logic gate output has changed state before the next clock pulse, you need to make the gate capacitances charge up quickly -- which means using a higher voltage than you could get away with at lower speeds. But 2x more volts means 2x more amps means 4x more watts.

Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.

Re:size vs heat

[soundsop]

Some clarifications:

Short-circuit current is only responsible for 10-20% of switching power. The rest is dissipated in the transistor through charging and discharing all the nodal capacitances (due to transistor gates, transistor diffusions and wiring capacitance). Since typical circuit styles are non-adiabatic, this charge/discharge power component would not go away even if we could completely eliminate short-circuit currents.

Making transistors smaller certainly reduces their gate capacitance but it also reduces their current drive by the same proportion. These two effects cancel each other out! So how can transistors get faster from generation to generation?

Transistors get faster by increasing electron mobility and/or increasing gate capacitance per unit area and/or reducing diffusion junction/sidewall capacitance per unit area/perimiter and/or reducing (local) interconnect capacitance since smaller transistors are closer together.

Re:size vs heat

[william_w_bush]

Great comment.
The unfortunate corrolary to:

Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.

is:

Smaller transistors will have less resistance, and so will dissipate more power.

Which is why the P4 prescott, while a marvel on the drawing board, is pretty crappy in reality. 90nm technology has largely been an attempt to find a happy medium between higher capacitance and lower resistance, both of which limit speed. The current "nucular age" of chips is a direct by-product of ignoring the drop in resistance until it was too late.

Also, at 4+ Ghz an current-induced EM field has many of the properties of a microwave beam, which can resonate, and essentially self-focus on any imperfections in the semi-conductor structure, essentially burning small holes in the chip, or causing signal noise unless perfectly grounded (which in itself causes inductive leakage). This is why intel and amd have speed-bins, because the chips with the fewest imperfections are able to perform at the highest clockspeeds without thermal or electric failure.

My point is, the mega-hurts race, even assuming one or more miracles of metal-oxide chemistry, is ending. I look forward to the multi-proccessing race which seems to be heating up, as a long-postponed, but neccessary next step. The sad obstacle holding back the day of 1000-thread chips has been programmers complete lack of willingness to move beyond the single-threaded debugging paradigm. As one myself, I understand why it's seen as hard as it is, but consider it more of a viewpoint shift, rather than an insurmountable increase in complexity. New languages/language changes will happen to simplify threaded programming, and new mechanisms like auto-synchronized data structures, self-unrolling iterands, and integrated message-passing stacks will replace old-standbys. The mega-threading doomsday scenario will fall along the wayside with other past programmer nightmares such as the death of the goto loop and the loss of direct memory access in java and higher level languages, left only as subjects of nostalgia.

Clockspeed is dead, long-live multi-threading.

Re:size vs heat

[elgatozorbas]

They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little.

Even if they don't EVER conduct (even a little) at the same time there will be dissipation because the capacitance is charged and discharged all the time. Each of these cycles implies that some positive charge moves between the power supply and ground with the capacitor as an intermediate step. This is why the dissipation is proportional to the clock frequency.

How did they do it?

[penguinoid]

"It was really simple," said the researchers at the University of Kentucky. "We siply asked the Flying Spaghetti Monster to fix the problem for us, and He did." </flamebait>

WTF is rapid thermal processing?

[arrrrg]

Anyone know? For once Wikipedia isn't much help.

PlayfullyClever, eh?

[Ospeovedizer]

So, did ScuttleMonkey not notice that the submitter's name was PlayfullyClever backwards? The one whose website says that the vast majority of /. posts are "blatantly plagiarized"? Although the news seems real enough to me, the submitter's name and website raised some pretty big alarm bells, especially since their site now says:

"okay, so we are going to win slashdot again, this time with a different game plan, keep your eye out for our new name.. it is VERY playfully clever."

Hmm... As I said, the news seems real enough, but the submitter is a fake.

Re:PlayfullyClever, eh?

[Anonymous Coward]

i checked the program at the 2005 International Semiconductor Device Research Symposium (http://www.ece.umd.edu/isdrs2005/program.html/) and sure enough, today at 4:35 PM, their paper is being presented: Dramatic Reduction of Gate Leakage Current of Ultrathin Oxides Through Oxide Structure Modification, Zhi Chen et. al, University of Kentucky

Re:PlayfullyClever, eh?

[Surt]

I don't really see how it's possible for the submitter to be fake. Either he submitted the story or he didn't. Apparently, he submitted the story.

Now, he might think the joke is that he's posting 'news' from a news aggregation site to a news aggregation site, but meta news is the only kind of news slashdot gets anyway, and that's what we come here for.

All in all, if he's scamming slashdot, he can only be doing it if EurekAlert is a fake, which it certainly doesn't look like at first glance, though I notice that in an unusual move for a meta-news site, it doesn't have links to originating information. That is somewhat suspicious. Still, if true, it's an incredible effort he's putting in just to scam slashdot stories.

Further, it would have to be a long term scam plan, since the UKY story in particular is real:
http://news.uky.edu/news/display_article.php?artid =844

So at best he's trying to build credibility as an article submitter for a later scam.

Physics

[kf6auf]

A quick lesson in quantum physics:
Basically, tunnelling occurs because an electron can get from one side of a potential barrier to the other without ever being in the forbidden region (the width of the barrier, where the potential energy exceeds the total energy of the electron) due to it existing as a wavefunction that does not collapse until you observe it. Anyway, the chance of an electron penetrating a simple potential barrier like the gate of a transistor is a function of the height of the barrier (voltage applied to the gate), the width of the barrier (gate length), and the energy of the electron (voltage across transistor + electron thermal energy).

So ways to decrease tunnelling include:

• Longer gate, but slower. Wanting smaller transistors and faster speeds is the whole reason we're having this problem.
• Increase gate voltage or decrease transistor voltage. Unfortunately these two are coupled. They might not exactly cancel each other out, but they make things difficult.
• Decrease the thermal energy of the electons. There are a couple ways to do this. One involves liquid nitrogen; the other involves something like making electrons climb further out of their holes to become free (fairly easy by introducing impurities into the silicon), resulting in less electron energy and so less tunnelling. Also less current in general though, so this might be prohibitive for some other reason.

Just my $0.02 since if I knew for sure I'd be making 6 figures somewhere and not applying to grad schools...

Re:On on U of K...

[Orgazmus]

C# _is_ a bit more high-level than C, or for that matter, assembly, which is the language they should be learning.

Other Applications

[EBFoxbat]

Assuming they really have discovered a way to lower power consumption (forgive me for not understanding semi-conductor principles) would it not be applicable to other semiconductors? I immediately thought about cell phone/mp3 player battery life and other such things. Even so far as to think about laptops. I (roughly) understand the not-so-much-wasted-power train of thought, and heat reduction from a CPU core and all, but wouldn't this have just as much effect on battery-powered devices? Or am I just being an ass again?

Re:Chip insulator sas capacitors?

[Antique Geekmeister]

Of course power flows through capacitors! You've got charges, you've got voltages, you have that charges flowing from one side to the other with a voltage on them in a certain amount of time, charge * voltage / time = power. If you couldn't transmit or modulate some power, you couldn't transmit or modify a signal. That's basic thermodynamics: if you can't transmit power, you can't transmit a signal.

The "work done" is, to some extent, recoverable when you change the state of the MOS transistor by discharging them. But that work is usually wasted and thrown away by simply discharging it to ground, then recharging it from the power supply, and that energy has to go somewhere and come from somewhere. But that can happen more in the power supply, and to some extent happens as electromagnetic radiation. You can't get rid of those two problems until you start playing with superconductors.

The heat and loss issues these researchers try to deal with are wasted work, trickle currents of keeping the transistor gate signals charged up as electrons leak away from the gate part of the transistor into the signal part of the transistor. They're nasty problems, taking constant current to keep even static signals active and wasting power as heat that has to be dealt with by some means.

Re:What does this mean?

[bbrack]

considering the fact that static (leakage) power should be
the real killer in microprocessors is the dynamic power - for wireless/dsp/ucontroller type applications, it could be pretty huge

honestly, the article has so few details it's impossible to tell what they're really doing, but i am pretty sure that most companies out there already use RTP on there gate oxide...

That's Gate Leakage, but what about SD Leakage?

[trigeek]

From the little information provided in the article, it appears that this takes care of the gate leakage problem, which is great! However, it doesn't address the Source-Drain leakage, which is a larger issue for current process technologies. Gate leakage isn't forseen to be a significant problem until 45nm.

This just tells us that future technologies are not going to have twice the leakage power as current technologies. This doesn't mean that future process technologies are going to have less leakage power than the current ones.

that is so very not right...

[YesIAmAScript]

Yes, power dissipated is V*V/R or VI And yeah, smaller transistors have lower resistance. But smaller gates mean less power, not more. You need less current to move the charge in and out of a smaller transistor (since the charge is smaller). So the "I" in the "VI" can go down. Well, that "I" is really a "V/R" (current across a resistance), so lowering that I really means you can reduce the "V". And since the total power is V*V/R, that means the total power used drops drastically.

Let me explain it a little better because I think I even confused myself.

Power is V*I. The I is V/R. Lowering this R means the V/R value does get bigger (current goes up). But also, since the I only needs to be sufficient to fill or drain a gate in a given amount of time (one cycle), you can reduce the V until V/R is a more reasonable value. And when you lower that V you're also reducing the other V in the power formula (V*V/R), so in fact instead of power going up, it goes down greatly.

For a much easier corollary, look at AMD's 130nm CPUs against their directly equivalent 90nm versions. The 90nm versions take half as much power.

Today's nuclear CPUs are mainly because there are so many transistors switching so fast in such a small space. If you built an old-type CPU using 90nm technology (like an Z80 or something) it would take far far less power than the old ones, which ran off of +5V (plug that into V*V/R!). Additionally, current CPUs have a lot of leakage current, something that CMOS didn't have a problem with until we got to sub 180nm processes. Compare a current CPU to an old NMOS or even ECL processor. You'll see how leakage was a problem before and how much of a savior CMOS was.

Additionally, the megahertz race is not over. It may not be the current concentration of vendors, but as chips go to smaller and smaller feature sizes, they naturally get faster. So even with little concentration on speed, we'll still see a rise in individual core speed.

A 1000-thread (simultaneous) chip is a ridiculous idea. That means you have to duplicate every transistor in the chip (like registers) 1000 times. That makes no sense. You will never reach the same speed as current single processor chips with a 1000-thread CPU (at least not right now). A small number of cores is a better idea at the moment.

Re:that is so very not right...

[william_w_bush]

a: I think I misspoke. When I said that at smaller feature size, resistance goes down, I was also considering leakage as a failure of resistance. You're right, the current 90nm designs do use less power, the amd design in particular because it uses SOI to compensate for increased leakage, while I don't believe intel has soi on its chip line yet. At these scales, execution tends to matter as much as size, and my earlier point of blindly scaling down in hope of finding more gains from the magical process shrink becomes much more of a challenge.

2: Also, in a 1000-thread chip, not nearly all the parts of such a chip would have to be replicated. Much of current superscaler design relies on scheduling for as efficient usage of pipeline segments as possible, to allow for the maximum chip usage. This same approach could work, by turning l1 cache into an effective register file, and simply having a part of the chip whose role is to schedule prioritized register sets to the requisite resources. At the extreme this could even allow decoupled pipelines, such that the decode, memory load and IO intructions are executed in a primary stage chip dedicated to preprocessing and high wait state instructions, then passed on via HS interconnect to 1 or more secondary processors to perform the actual arithmetic, even allowing whole chips to perform the ancilliary functions such as the sound or GPU today, while being tightly coupled to the memory and processor state.

My point is that from this point on, threading will scale much faster than clockspeed. Even now, it is easier to make a second core than to double the clockspeed for the faster processors, and unless the leakage issue from tfm is solved soon this won't change.

Plus, once you have the right programming language support, with auto-parallelizing iterands, and self-dispatching async subroutines, who needs a fast chip, the actual instruction pointer, the current limiting factor, becomes meaningless, with all actual work being done parallel automatically, dependencies and resource sharing solving themselves by language design. A 1Ghz multithreaded chip can be as effective as a 4.0 Ghz prescott today, without even including the specialized instructions (SIMD, fast fp) that can boost actual efficiency through the roof, and be compiled in as static asynchronous subroutines dispatched parallel to the "main" thread.

Re:that is so very not right...

[aminorex]

> A 1000-thread (simultaneous) chip is a ridiculous idea.

Strong claim. One must ask: Why?

> That means you have to duplicate every transistor in the chip (like registers) 1000 times.

And this is bad... how?

> That makes no sense.

It makes enormous sense when you're running 1000 threads!

> You will never reach the same speed as current single processor chips with a 1000-thread CPU
> (at least not right now).

Naturlich, since the latter is a figment. But supposing it were real, one would have to ask: Why not? You can't seriously intend that it would be impossible to run each thread at 4 or 5 MHz, as you seem to be saying, so I can only infer that your meaning is not clear to me.

Since threads block so often, by the way, there is an optimal ratio of register files (thread states) to execution units, which will vary with load characteristics and degree of parallelism. System architectures that allow threads to avoid blocking will get more execution per transistor. One good way to do this is to provide hardware call/cc support, but it fails the goal of reducing register realestate.

Terrible news for cooks

[petantik f00l]

This news has made me very depressed.

how can I now be a cook at the same time as programming?

Before my Pentium 4 generated heat enough for frying eggs and I'm sure in a few years I would be looking for recipes suitable for heat generated by nuclear reactor( charcoal egg comes to mind) but now me dream is gone. Damn you University of Kentucky researchers. I hope we never meet