Reduce Transistor Power Consumption

revelCyllufyalP writes to tell us that University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors. From the article: "In order to improve computer chips' performance, transistors' size and gate insulators have to be continuously shrunken so that more components can be packed into a single chip. Computer chip producers were hitting a wall in downscaling the transistors and gate insulators because of their inability to reduce the leakage current of the existing gate insulators. This new technique will help the chip producers to develop more powerful chips with low-power consumption."

Comments

Prior art?

[Dirtside]

University of Kentucky researchers have discovered a way to reduce the overall power consumption of transistors

Wayyyy ahead of you.

Where's the news?

[Anonymous Coward]

As probably one of the few semiconductor geeks on /., I have to say: Where's the news? Gate dielectrics are always made with rapid thermal processing on current technologies. Basically, stick a wafer in a chamber, flow some gas, turn on some super-high intensity
lamps, heat the wafer to >1000C for a very brief time, grow a few atomic layers of silicon dioxide (or some variant that includes nitrogen), turn off lamps, cool wafer, take it out of chamber.

From what little info is in the press release, it doesn't sound like they're doing anything revolutionary, so I'm curious why they claim they can reduce gate leakage by so much.

size vs heat

[esac17]

What you have to remember about heat is that electronics only get hot because they are never perfect conductors nor perfect insulators {though we can make nearer-perfect insulators than we can conductors}. A perfect conductor will never get hot, no matter how much current you put through it, because the voltage drop across it will be nil and power = voltage * current. Nor will a perfect insulator, because this time, the current through it will be nil.

CMOS is based around two transistors, a P-channel FET which goes conductive when the gate is driven low, and an N-channel FET which goes conductive when the gate is driven high. The P-FET is trying to pull the output high and the N-FET is trying to pull it low. Both the gates are joined together, and this is the input. This is a simple NOT gate.

For a NAND gate, where any input 0 will drive the output to a 1, we have several P-FETs in parallel trying to drive the output high, and so many N-FETs in series trying to drive the output low. Each P-FET gate joined to an N-FET gate is one input. When they are all high, all the N-FETs turn on allowing the output to go low; when any one is low, the chain of N-FETs is broken, one or more P-FETs turn on, and the output goes high. For a NOR gate, where any input 1 will drive the output to a 0, we put the Ns in parallel and the Ps in series. You can make AND gates from NAND+NOT, OR gates from NOR+NOT, and any other combination you like. In fact you really don't need both NAND and NOR, because you can make either one out of the other; but it turns out they're equally as easy to make as each other in CMOS {not like many other technologies}.

In an ideal world this would never dissipate any power, since the input cannot be high and low at the same time so only one of the transistors will ever be on. In practice what happens is that the gates act like capacitors which take a finite time to charge and discharge. They do not switch instantaneously from conductive to non-conductive. So one stops conducting while the other is starting to conduct, and for a brief instant while the inputs are changing state both transistors are conducting a little. It's not a dead short circuit of course, otherwise something would give way ..... hopefully a fuse.

Now every time something changes state, you get a little pulse of heat. Which is why fast processors need cooling. Additionally, to make sure that the logic gate output has changed state before the next clock pulse, you need to make the gate capacitances charge up quickly -- which means using a higher voltage than you could get away with at lower speeds. But 2x more volts means 2x more amps means 4x more watts.

Smaller transistors should have less gate capacitance, and so be capable of switching more quickly.

Re:How do you reduce tunneling current?

[soundsop]

It's easy to reduce the tunneling current through the gate. All you have to do is increase the thickness of the insulator. Unfortunately, this has the detrimental effect of reducing the effective capacitance of the gate, which in turn lowers the amount of current conducted by atransistor of a given size (lowering the current also lowers the speed). To make up for the lowered gate capacitance, researchers have been trying to increase the dielectric constant of the insulator. I'm guessing that they're proposing a method to increase the dielectric constant of the gate insulator. The devil is in the details of improving the dielectric constant without screwing up later processing steps or reducing the mechanical integrity of the wafer, etc.

Summary:

1. To lower gate leakage simply increase dielectric thickness.
2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
3. Profit.

PlayfullyClever, eh?

[Ospeovedizer]

So, did ScuttleMonkey not notice that the submitter's name was PlayfullyClever backwards? The one whose website says that the vast majority of /. posts are "blatantly plagiarized"? Although the news seems real enough to me, the submitter's name and website raised some pretty big alarm bells, especially since their site now says:

"okay, so we are going to win slashdot again, this time with a different game plan, keep your eye out for our new name.. it is VERY playfully clever."

Hmm... As I said, the news seems real enough, but the submitter is a fake.

Re:How do you reduce tunneling current?

[saifatlast]

I'm no expert, but even I can see that you missed a step here. Here, I'll fix it for you.

1. To lower gate leakage simply increase dielectric thickness.
2. To make up for lost speed due to higher dielectric thickness, increase dielectric constant.
3. ????
4. Profit

Hope that clears things up for everyone.