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AMD Licenses Z-RAM Technology
ZuperDee writes "It appears AMD has licensed Z-RAM technology from Innovative Silicon for possible use in future processors. According to the article, this could lead to caches about 5 times denser than the SRAM that is normally used right now. C|Net says they will probably make the announcement on Monday."
We have run out of ram letters!
It's a single-transistor capacitorless memory cell using the "floating body effect" of silicon on insulator (SOI) devices. Presumably stored charge in the gate affects the operation of the transistor in a way that can be used to store and read a bit, but I didn't feel like registering to read the white paper. The new memory should be six times denser than SRAM and twice as dense as DRAM.
"Is life so dear, or peace so sweet, as to be purchased at the price of chains and slavery?" - Patrick Henry
This is another article covering the licensing which was on digg.com earlier http://www.eetimes.com/news/semi/showArticle.jhtml ;jsessionid=V2AQAAYC3GVIQQSNDBESKHA?articleID=1771 01749
We still got all the letters in Unicode...
It's better to be the foot on the boot than the face on the pavement. ~~ tkx Kadin2048
http://www.google.com/search?q=zram
5 18&id=5434
A nice techy article about how/what makes ZRAM special. It goes in-depth about the things you mention. http://www.cieonline.co.uk/cie2/articlen.asp?pid=
Obligatory Wikipedia Link
[Fuck Beta]
o0t!
They can, but probably won't.
As many like to point out, Intel often shows a "Not Invented Here" attitude.
It took a while for Intel to adopt copper interconnects, and they did that quietly when they finally caved.
As far as I know, they still aren't using Silicon On Insulator.
"Everything you know is wrong. (And stupid.)"
Moderation Totals: Wrong=2, Stupid=3, Total=5.
Should have gone AMD, Steve.
Apple's already been down the road of choosing the apparently spiffier processor from a vendor that wasn't able to deliver in quantity. If AMD becomes the better processor choice in the future, then I'm sure Apple will switch again.
-jcr
The only title of honor that a tyrant can grant is "Enemy of the State."
Organ Dealer: Z is just as good. In fact, is better. Is two more than X.
Rambus is not a way to store information on a chip, it is a proticol designed to transfer data between storage spaces using packets and a bus. This is a constrast to SDRAM which transfers data by synchronously indexing then caching a strip of data and copying it to or from the chip's cache. Z-Ram on the other hand is a way to store information on a chip just like DRAM or SRAM. Z-Ram makes no demands as to how information is transfered, it may theoretically be done using the Rambus system (making RZRAM rather than RDRAM) or more likely using the Double Data Rate Synchronous Ram system (making DDR SZRAM as opposed to DDR SDRAM). In this case it is not intended to be used as system ram at all but on-die cache. Thus it will not have to use either of these systems since it (as cache) will only need to interface with the CPU and MMU. Such a system will have no impact as to what ram someone may use and will make no archetectual differences outside the die. Thus the Rambus comparison is completely pointless. If you had even read the summary properly you would know that.
When Argumentum ad Hominem falls short, try Argumentum ad Matrem
Well, it's a sign that market leader Intel has over the decades drifted more towards marketing machine mentality, while challenger AMD has stayed somewhat truer to its engineering roots.
Intel went for Itanium, while AMD went for 64-bit x86.
Intel went for Rambus, while AMD went for DDR and HyperTransport.
If you look at the multicore technology AMD is researching, it looks better than Intel's multicore.
I'll acknowledge that Intel recognized the value of wireless ahead of AMD, although dedicated wireless chipsets are obviously better than Centrino anyway.
I'm just glad that healthy competition is there, to make us consumers the ultimate winners.
To get into a console, you can't win if you fall into categories 1 or 2. If the Cell were that expensive or underperforming, people wouldn't be putting it into consoles.
Now, there is one thing about the Cell you missed - It's a special-purpose processor designed for raw floating point performance. 8 of the cores can only do basic streaming floating point (although they do it EXTREMELY fast), the remaining CPU is a VERY stripped down PPC.
So for a gaming system or DSP, the Cell will kick ass. For general purpose computing, it's going to suck.
retrorocket.o not found, launch anyway?
In a nutshell, on a CMOS transistor on an SOI process (such as used by AMD and IBM, but not used by anyone else that I can think of... Intel, TI, TSMC, NEC, Samsung, etc), the delay of the transistor (how fast the transistor is) depends on the history of the signals that were applied previously to the terminals. So the transistor has a memory of previously applied values. Which, now that I write this, seems like it's obvious that this would make a possible memory storage element, but normally this "feature" is a major pain - because it's difficult to track the history of signals on a transistor using current CAD tools for, for example, determining the speed of the final design, you have to assume the worst case (so that your chip works no matter what).
0 0076+body+hysteresis+soi&hl=en )
So normally this "feature" is considered a liability, or at least something that designers wish could be an asset but which is too hard to utilize effectively and is thus ignored.
In more gory details, this exerpt from EETimes explains it pretty well:
( http://ww.eetimes.com/issue/bb/showArti...D%3D573
In partially depleted MOS transistors -- the only kind used in production SOI today -- the body of the transistor is a small, electrically isolated piece of silicon trapped between the active portions of the transistor and the insulating layer underneath. If this body is allowed to float, it will take on a voltage determined by the capacitive coupling between it and the other portions of the transistor. But the voltage -- or, more properly, charge -- on this floating body can affect threshold voltage, and hence the drive current, of the transistor.
Ideally, the floating-body effect can deliver a formidable performance gain. Two circumstances arise from that gain, Soisic's Pelloie said. First, the voltage on the body influences the transistor's threshold voltage. "If you switch the gate of the transistor from off to on, then the body potential increases, which yields a decrease of the threshold voltage and then an increase of the drive current," he said. "The switch is then faster than in the bulk CMOS case, where the body is grounded."
The second effect is another mechanism for influencing the threshold voltage. "When you use stacked transistors in a gate, like NAND, NOR and any other combinational gate with multiple inputs, the body-to-source voltage of the transistors corresponds to a forward-bias condition, and the threshold voltage is lowered," Pelloie said. "For bulk CMOS or in a grounded-body situation, if the source has a high voltage value, for instance Vdd [the power supply voltage], the body source voltage then becomes - Vdd and the transistor body source junction is reverse-biased." That increases the threshold voltage and lowers the drive current. Analyzed at the circuit level, he said, these two SOI advantages are combined and globally yield a higher-speed operation.
But there is a catch to these threshold-voltage-lowering mechanisms, as Pelloie explained: "Since the body is floating, it follows the variation of the other terminals of the transistor. The body voltage never keeps the same value, as the transistors are, most of the time, switching in normal operation mode. This results in what we call the history effect: The propagation delay and some other features of the gates depend on the history of the signals applied to their terminals."
-------- end EETimes snippet -----
It will be interesting to see how this particular use of the floating body effect scales as we continue to move to 45nm and beyond. It will also be interesting how it handles low-voltage quantum-induced soft-errors. Also, similar to DRAM, this type of memory will need to be refreshed - if AMD uses it in a design, it will interesting to see how the impact of refreshing, and trying to read a very small effect and amplify it to make a signal will impact the speed of the devices when used in a large cache array.
Note that if ZRAM works, it would let AMD put something like 4X as much cache on their chips in the same die area. This indeed would be quite a competitive advantage.
But why do people assume this will work? There's a couple companies trying to do this stuff (T-RAM is another) and none have succeeded yet.
It has proven to be difficult to get this kind of technology working in production chips. The main difficulty is that process control becomes very very important. Your yields drop through the floor.
Additionally, note that any 1T transistor technology is inherently a stored charge device (like EPROM, EEPROM or flash memory but different). The problem is that transistors on chips are getting so small that they have less than 100 electrons in the gate of a transistor. So your insulating ability becomes very important. Your chip is designed for electron mobility that electrons can flow around a fairly long loop (the instruction execution path) 1 million times in 1 millisecond. And now you have to make sure that 100 electrons sitting in one place don't leak out in that same time.
It's a challenge. It might be possible. I don't see any particular reason to think that AMD is going to be the one to do it though. Intel are wizards at process technology, as evidenced by their movement to 65nm before AMD. They don't happen to use SOI though, that's about the only advantage AMD has in this situation that I can see.
Anyway, I do like AMD (I'm typing this post on one), but them licensing some unproven technology from a 3rd party is no kind of condemnation of Intel or Apple's choice of Intel.
http://lkml.org/lkml/2005/8/20/95