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Magnetic Processors - Computing's New Future?
metalcoat writes "For the first time researchers have created a working prototype of a radical new chip design based on magnetism instead of electrical transistors. As transistor-based microchips hit the limits of Moore's Law, a group of electrical engineers at the University of Notre Dame has fabricated a chip that uses nanoscale magnetic "islands" to juggle the ones and zeroes of binary code.
Wolfgang Perod and his colleagues turned to the process of magnetic patterning (.pdf) to produce a new chip that uses arrays of separate magnetic domains. Each island maintains its own magnetic field. Because the chip has no wires, its device density and processing power may eventually be much higher than transistor-based devices. And it won't be nearly as power-hungry, which will translate to less heat emission and a cooler future for portable hardware like laptops."
True, an ideal CMOS doesn't have any leakage; these days, however, the very small feature sizes translate into more and more leakage, mainly because of the tunneling effect. It's not uncommon for the leakage power to be one fifth of the entire power consumption; unfortunately, with future generations, this will only get worse.
The Raven
Wikipedia entry for Magnetic Bubble memory. I worked on Magnetic Bubble memory at IBM san jose, and the wired article sounds like this is the nano-scale version of this with some big improvements in how they are manipualted. Back then the "bubbles" were a few microns in size. You patterns permaloy onto the surface of a magnetic material. Usually this was a long loop of almost touching chevrons or T-shaped permaloy elements. the bulk materila was polarized one direction (normal to the chip) and inversions in this formed round "bubbles" for reasons simmilar to surface tension these bubbles were stable in one size and liked to stick to the chevron. Under a polarized light microscope you could see the "bubbles" in contrast sticking to the chevrons, giving them their name due to their appearance. one bubble stuck to one chevron. and the presence or absense of a bubble on a chevron was a 1 or 0. in some fancy schema the bubbles could hold internal higher order domain structures to encode more than one bit per bubble but these were never made practical.
A rotating magnetic field transverse to the chip would cause the chevrons to act like little iron bar bagnets pulling the bubble from one side to the other. because the chevron shape is asymetric it acted like a rachet and would only move the bubble unidirectionally. If the field was strong enough the bubble would then "leap" to the next chevron. Under the microscope you saw marching "bits" moving along. so you could move all the bit patterns like a train along the tracks in a bulk matterial with one layer of passive patterning. at one point in the loop track you placed a reader and a writer. this way you had sequential access to any bit and could inject or delete bits in the train.
When the power went off the bubbles stayed put.
It never made it to market (fuji made some) because it's niche was too small. it was slower than ram but faster than a hard drive. it was cheaper than ram but more expensive than a hard drive. At the time it was denser than ram but less dense than a harddrive. Thus it's only use was as a cache between ram and harddrives and in applications where robustness and non-voltility would be valuable like high-radiation sattelites and point of sale terminals. The latter market was eaten by EAROM and then flash memory.
this new material sounds like it uses simmilar concepts but is much smaller and actually performs bubble logic. Not sure about where the clock comes from: perhaps it's still a rotatin mag fiield?
Some drink at the fountain of knowledge. Others just gargle.
Specifically they are developing to the International Technological Roadmap for Semiconductors (ITRS), which is produced by the Semiconductor Industry Association (SIA), of which Intel, AMD, IBM, etc are members. This is the little-known [by the public] pre-competitive stage of the semi-conductor industry in which they all get together and collaborate on developing a "best available industrial consensus" on the way that the industry should move forward (choice of semiconductor technologies, etc).
This lecture by Sir Maurice Wilkes http://www.cl.cam.ac.uk/~mvw1/Progress_in_Compute