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Who Makes Custom Chips?
toybuilder asks: "I have an idea for a neat consumer product that could benefit greatly from a really simple bare-die chip to reduce cost and size. I took a VLSI and chip design class back in college about 10 years ago, so I know how to design the circuit I want in CMOS. Now, I'm sure there must be fabs for older-generation designs (maybe in China/Taiwan) that I could have such a chip made -- I've seen bare chips in musical greeting cards and in tiny toy gadgets. How do I go about making my chip design into reality if I only want to make a fairly short run (a few *chips* during development, and maybe a 6" wafer's worth of the final design)?"
http://en.wikipedia.org/wiki/FPGA FPGA
Have you considered an FPGA, since it's a limited # you want? My knowledge of such things is severely limited, so forgive me if this isn't appropriate.
Unless you're making 1 million of them, it just doesn't make sense. FPGA's and CPLDs aren't just for prototyping anymore, many small-run products use them.
Hell, depending on the simplicity, are you sure you can't get away with a pic microcontroller? That's what the OTPs are for, after all.
If you can do your design in software, a PIC microcontroller http://www.microchip.com/ is about the cheapest option.
Unless you're ordering a hundred bazillion, you don't get custom chips made, you use mass-produced programmable chips. Making custom chips requires a hugely expensive setup process, so it's extremely unlikely to be cheaper or better in any way.
perhaps a university with a fab would be willing to let you make a run or two of your chip, although they might want to charge you a hefty price. maybe as a lab project or something a few students could use your design and make the chips. i know the university i attend (RIT) has a fab that can manufacture 6 inch wafers.
Heuristically programmed ALgorithmic computer
I recall IBM has a program, where they will make your custom chip. This might have been something in the past, but I think they might still have it.
http://www-03.ibm.com/chips/asics/
SimonTek
Any decent fry cook...
Look into FPGAs. Xilinx Spartans on boards with a bunch of other electronics might help in testing. Learn Verilog or VHDL and with some software you'll be designing some stuff easily. ModelSim is great for simulating and XilinxIse is a nice IDE to get started. The whole setup might cost a few pennies, but you can keep reprogramming and testing it until you decide to go further. There are lots of resources for Verilog and VHDL and Verilog is open. However, you're still gonna have to plunk down some money on proprietary software.
Design it using a HDL and you won't have to worry about who builds it. If you can find a way to raise the $1mil in NRE for an ASIC, you're ready to go. If you can't, then you can just use the smallest FPGA your design will fit in.
You want MOSIS. Providing small volume chip fab services (via short ganged-mask wafer runs at flexible mainstream fab houses) for decades now, Mosis is exactly what you want if FPGA and a programmable microcontroller aren't what you really need.
If you can't do it something like a Microchip PIC, then try a Xilinx FPGA.
Most people will say FPGAs but thats different than real hardcore VLSI silicon.
I did such a search a while ago when I had an idea incorporating an ARM core and some other stuff. There are VLSI-named mailing lists or groups where I found the names of such companies who do provide this service. For low volume theyre really expensive mind you.
I forgot where I saw that but the prices put me off. Do your own googling before posting to slashdot.
"Give orange me give eat orange me eat orange give me eat orange give me you." -Nim Chimpsky
If you want to attempt it, MOSIS does small run fabrication by batching up small runs onto a single wafer and running them through commercial fabs like IBM and TSMC. The prices aren't out of reach.
However, you should remember from the VLSI class you've taken that it may take several runs before getting anything usable. Unless your design has some aspect that makes using a FPGA infeasible, you'd probably be better off with the FPGA. As I recall, a couple of FPGA vendors can also do conversions from FPGAs to hard-wired ASICs if you desire it later.
One of the most expensive parts of a new chip design is having a set of masks made. I've heard these can cost millions of dollars on a typical VLSI design, but let's be conservative and say you can get a simple set for $50000. If you make 1000 chips, your cost per chip is $50 in masks alone. This doesn't even include the cost of silicon, fab fees, and so forth.
If you want to go cheap, several companies make low-cost microcontrollers. A quick hop over to http://www.ti.com/msp430 shows that you can get a 16MHz, 16-bit microcontroller with 128b RAM, 1K flash, analog comparator, slope AD converter, watchdog timer, 16 bit timer with 3CCR's, 16 IO pins, and brownout reset for only 90 cents each. I don't know what you want to do, but I bet you could do it with a chip like that. Plus, TI isn't the only company making stuff like this. If you shop around a little, you can probably find something for as little as 50 cents.
Shhh. Your wife might hear you.
FPGAs are far cheaper than custom silicon for anything other than a massive production run, so the replies elsewhere are very sound advice. However, a small microcontroller (an eight bit device like an AVR or perhaps one of those new 32 bit ARM7 micros) will be significantly cheaper again. Not knowing anything about your requirements or design I can't say whether a microcontroller will enable you to achieve the desired results, but the cost advantages would make this well worth investigating.
The newest microcontrollers are incredibly capable devices, and have great peripherals. Even if you have to make a design compromise or two, or use some extra (non-custom) chips, software on a standard micro might be the cheapest option.
I can't imagine what you could possibly want to do that you couldn't do with a fifty cent one-time programmable microcontroller.
Conclusion: the Empire squashes the Federation like a bug. Accept it.
This company will make chips to order if you buy enough.
CRUNCH!
I used to work at SNF. Industry and small businesses were also allowed to use the lab. I has some very modern equipment but it is mainly for prototype. Once you have a working sample it then can be sent to a fab house for a production run if you get funding. It is not exactly cheap but a small project could be done w/o alot of investment. It all depends on how complicated your process is.
I have secretly hidden some mispelled words in this post. Can you find them?
Even for ooold technologies, the mask set cost will run into the $10k-30k range.
Each development version will require a respin of at least one or two of the masks in the mask set.
Even old fabs won't do such a low final run quantity either.
Universities won't be cheap either... unless you happpen to be making the chip as a design project while you are taking classes there.
(I went to RIT and did projects in their fab.)
Everyone else here is pretty much right that MOSIS - style group runs or PLD/FPGA/FPSLIC or microprocessors are the way to go for such small quantities.
Atmel does FPGA -> ASIC conversions as do a few other companies.
At one time you could do a multi-project Mosis wafer. No masks are made,
p w_sched.html
the data is directly written to the wafer. Each project makes up 10 to 20 die on a large wafer. Flextronics was doing this for a while too, but I believe they have moved to a different business model. Check out the following link to IBM talking about their current Mosis schedule. I'm sure more info is there on the website.
http://www-03.ibm.com/chips/asics/foundry/tools/m
Good Luck
Honestly though, ASIC's are truly dead but for many applications, and especially consumer applications.
From your post, you seem to be underestimating the amount of effort required to correctly design an ASIC. Verification that your hardware design is correct is an extremely difficult task and the fab costs will mean that you won't often be able to revise your design based on tests of the real world device.
If you choose an FPGA, as others have mentionned, you'll be able to inexpensively implement your logic on the device at a very low cost (for mid-low volumes). In addition, since it is field-programmable, you can revise the design, issue bugfixes, and add features very easily in most cases. If your sales ever end up reaching high volume, you will likely be able to easily transition (mostly) to a custom die ASIC when it becomes economical for you to do that.
To give you an example, the company I work for spent millions of dollars to design a custom processing ASIC for some of our hardware. Our newer boards include a reconfigurable processing FPGA and were developped for a fraction of the cost.
on search query "fab your own chip", FWIW, I have NO idea about this ad, just found it. Spiffy domain name though
http://www.makeyourownchip.com/
If this guy wants bare die, it's because he's building a complete system on a chip for some specialized application. That probably means including some analog and power components. An FPGA may not be suitable.
And even if it sounds like a really good idea, I don't want anyone running off to the patent office or anything, OK?
---
I'm not an electronic engineer, but I play one at work.
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Stay sentient. Don't drink bad milk.
Actually, Taiwan has one of the largest fabs in the world. you might have heard of them - TSMC.
If you're in Canada, look up CMC - they fit several designs on die from different universities which makes it cheaper to manufacture because you'll no longer have to pay for more prototypes than you need to made.
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Everyone is talking about designing and fabing the chips. However, you also need to test them once they are fabbed. That is another big effort - you will need to generate the test vectors, then design an interface board, plus a whole lot of work. And the cost is also significant - it could easily cost $10000 for a loadboard. In fact, high end sockets for testing easily top $3000. Add $100/hour of equipment costs, and you start to get the idea .For the big semi houses, testing the manufactured chips costs more than the actual manufacturing.
Once you need more than a few hundred units, then you can consider going through all that effort.
No, I don't trust in god. He'll have to pay up front, like everybody else.
Unless you're making zillions, a microcontroller is the only way, unless you need the speed of an FPGA.
Package sizes are down to almost die levels these days, and die are available from some makers if you really need them.
If you need lots of analogue functionality, look at the Cypress PSoc range.
Hi FPGA field apps guy here - an Altera Cyclone EP1C3T144C8 (3000 odd LEs - an LE is a programmable register and some combinatorial logic) will do the trick pretty cheaply with an EPCS1SI8 (FPGA's are SRAM so you'll need a flash config. Whole solution about $16 for both chips at low volume. See altera-dot-com and look for QuartusII web edition . This free download will let you put your design in schematically or via an HDL such as verilog, or VHDL. At last a question on Slashdot I'm well qualified to answer. :)
Almost every reply seems to think that the only chips in existence are digital. If you are thinking of a digital design then, as the others said, FPGAs are the way to go - certainly for prototyping.
If you need an analogue device or want chip scale packaging of your device, then an asic would be more appropriate. It is possible that FPGAs are available in very small packages but I'm not very up on that.
If you're in Europe, the Europractice scheme provides access to Multi-Project Wafer (MPW) runs to reduce overall fabrication costs. They also provide the software and design kits that allow you to make your designs.
My price breakdown for a 10sqmm chip in the AMS C35B4 process (0.35um, 4 metal, 2 poly, high res) with 20 devices in CSOIC28 packages:
Full Europractice membership (annual): €900
Cadence IC package single license: €1800
Cadence IC package maintenance (might not be applicable for the first year): €1150
10sqmm of AMS C35B4 silicon @ €720/sqmm: €7200
20 packages @ €52/package: €1040
Total: €10,940 or €12,090
Non of the prices include any local taxes.
They also do low volume production, but I don't know anything about the pricing.
So how to bring that down? You could save €1800/€2950 on software by using free alternatives such as on this
page. You'd have no end of problems with design rules and layout vs. schematic verification but it would be possible. Normally I'd say allocate two months of hard graft at the very least using the normal tools and with support from someone who knows what they're doing. With inadequate tools (no design rule check/layout vs. schematic) you would have to at least double it and you still might have errors.Don't be influenced by your opinions of current design processes. We use a 0.35um process all the time. It's perfectly adequate for what we want to do - in fact in many ways it is better than smaller processes for us. You could save a lot of money by going to a coarser process such as the AMIS 0.7um (2 metal, 1 poly) at €360/sqmm or the AMIS 0.5um (3 metal, 1 poly) at €420/sqmm - both with a smaller minimum size at 8sqmm. Silicon cost would then be €2880 or €3360 compared to €7200. 8sqmm is quite a lot really.
Ultimately, you need to decide what you need. If you need analogue circuitry but don't need linear capacitors, go for the cheapest process. If you do need linear caps, you'll have to use a process with 2 poly layers. If you want digital as well, go for something finer and with more metal layers
Do you have any better hostages?
You didn't really supply enough information for a definitive reply, so I'll make some assumptions as I go along.
First, I don't understand how a "consumer" product could need only a wafer's worth of chips. In the industry, consumer == high volume. I assume, therefore, that this isn't a commercial venture, but a hobby of some type. (Oh, and a word to the wise: Don't go around anyone in the industry with the line about the fabs for older-generation designs being in Taiwan--you'll be marked immediately as either a newb or an idiot. TSMC and UMC are leaders in the semiconductor foundry business, not also-ran bottom feeders.)
Since you mention a VLSI class I'll assume you want a purely digital chip, and that you have no special needs (ultra-high speed, analog circuits, etc.). As others have suggested, if you're doing this yourself an FPGA or microcomputer is the obvious way to go, but I'll add another reason why: A single individual, working in his garage writing Verilog or VHDL from scratch, cannot conceive and design enough VLSI logic in a year to fill up even the smallest ASIC in any process even remotely modern. (Even a five-generation-old IC process is good for 25k gates/mm^2, with the smallest die typically 5 mm^2 or so; that's a lot of Verilog!) So even if you did an ASIC, the size of the die likely would be determined by the number of pads, not the logic--a so-called "pad limited" design--and so isn't likely to be economical to produce. So, FPGA.
What you're looking for, you say, are "bare chips." Your biggest challenge isn't going to be the logic design of the chip, it's going to be this--finding a vendor that will supply bare die FPGAs that you can flip-chip or wirebond and pot to your substrate (whatever it is). Discuss the issue with your local Xilinx and Altera reps. Packaging is a far bigger problem for you than your logic design, especially if you care--maybe you don't--about nasty environmental conditions like humidity and vibration. Do a google search for "custom IC packaging" and look for a custom manufacturing house that will do this for you. Bring to the first meeting a wirebonding diagram (a drawing showing the locations of all the pads on the die to which you want to connect) of your FPGA, a technical description of the substrate material (manufacturers' trade names often suffice), and clues to your overall plan that you can share with the people making your product. If you're doing flip-chip (a.k.a. C4, or other names) packaging, be advised that the die must be specifically designed for such packaging; your task, should you choose to accept it, is to find a mutually-acceptable packaging method between yourself (who has the end-product vision), the chip vendor (who has to supply the chip), and the contract manufacturing house (who can only do the packaging/mounting techniques for which he has the materials and equipment). Oh--and be sure that the FPGA vendor supplies you TESTED bare die--not just bare die.
You may wish to ask the FPGA vendor about "chip-scale packaging" options for his part. Often these packaging schemes, which can look like bare die to the naked eye, are simpler to use than true bare die.
Finally, don't forget that you'll want the contract manufacturing house to test your product after packaging your chip, to ensure that you get good working product and not just high technology waste. Provide him a written test procedure, which typically exercises each pad he was to connect.
Best of luck, and welcome to engineering. Isn't it fun?
I went to RIT for Economics. Silly, I know, but it was 20 years ago, when I had to work the early shift in the VAX labs so I could play Moria before 8:30.
I've seen it mentioned before in this thread, ask and include students, you never know what will happen until you do.
I forgot what I wanted to say, but honestly, it was important.
How can you NOT know about this:
http://www.mosis.org/
Wow, I didn't realize that my submission was getting accepted! Sorry for the late response.
MOSIS is exactly what I was trying to remember from my college days. I only had exposure to this back in college, so I didn't remember the prices being so high. Maybe it was subsidized a lot back when I was doing it for educational use...
What I have in mind is a chip that conmbines very simple finite state machines, some additional counters and logic gates on the digital side. Imagine a 8" x 8" breadboard full of 74-series DIPs, and you'd get the basic idea of the low complexity on the digital side.
On the analog side, I want to have some caps, opamps, and very beefy output drivers.
The whole thing is going to be "thumb sized", including the battery and the output device, so there's not a lot of room. And smaller the better -- so that's why I was thinking of bare dies.
It looks like I should first try to find a mixed-signal programmable device and hope that there is a chip-scale packaging.
I had dismissed ASIC because they seemed like overkill. A tiny uC might be okay in light of the high development costs of a chip.
Thanks guys. This has been great!
Or bare-die op amps and a microcontroller. The cost of die-bonding bare dice to a small PC board and epoxy-potting them is waaay lower than any kind of custom chip, and is very compact, with low up-front cost compared to custom chips.
The previous poster's suggestion is, of course, even better IF you can find a stock chip that has the requisite analog capabilities. You can do a lot with small-outline surface-mount packages for op amps and microcontrollers; there are many inexpensive, powerful options there. The cost of rolling your own chip is SO high that it justifies expending great effort in trying to do the job with off-the-shelf parts instead. (And you'll want to prototype the device for testing anyway prior to committing to wafer fab, so you'll likely do this step anyway.)
PIC processors are great, and the Atmel AVR series microcontrollers (which I use for projects written in C) are amazingly powerful, quite cheap, have on-board EEPROM and flash, and have some have built-in ADC and DACs, and a lovely small-footprint RTOS, AVRX, plus an excellent development board. You might also want to check out SDCC, the Small Device C Compiler, which supporrts lotsa different controllers. Write what you can in C, optimize the critical parts in assembler.
Don't underestimate the power of digital signal processing, even using standard microcontrollers, as an alternative to a large cluster of analog parts. And best of luck. The technical end is the easiest part; marketing your wonder widget will be much harder, as it deals with human irrationality and whim instead of clean, logical electronic design (you can see why I'm an engineer instead of a salesman...)
"My strength is as the strength of ten men, for I am wired to the eyeballs on espresso."
The NRE (non recuring engineering - in this case likely only mask genereration) on a project that does not hav significant volume would be so stagering that you wouln't be able to do it. You might want to try "contracting" with a local university. Back around 10 years ago when I graduated there was a VLSI course atht he University of New Hampshire as a senior project I did a VLSI chip in 2 um technology (which was way below the cutting edge at the time). These chips were fabbed in a short run with Mosis. I think we got back 4 packaged dies. Perhaps you could work with a student doing a similar project (and possibly help fund it) by cramming on a secondary function which can be selected with a bondout.
As a proof-of-concept this would work great...but you would likely be limited to one die in the end.
>> I took a VLSI and chip design class back in college about 10 years ago, so I know how to design the circuit I want in CMOS. Now, I'm sure there must be fabs for older-generation designs (maybe in China/Taiwan) Hate to break it to you.... 10 years is two generations ago.... China/ Taiwan have progressed a little bit in the last 10 years....