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Intel Ships Core Duo-based Xeon

Posted by ryuzaki0 on from the new-chips dept.

diegocgteleline.es writes "According to The Register, Intel has begun shipping a power-efficient dual-core "Xeon LV" and claims that it consumes no more than 31 W running at 2 Ghz, with a 667 Mhz frontside bus and sharing 2 MB of L2 between the two cores. The new chip has "four times the performance-per-Watt of its existing 2.8GHz LV Xeon CPU", not surprising given how slow and power inefficient those CPUs were. While this looks like a move to make AMD shares continue yesterday's tendency, it looks like Intel is starting to catching up?"

16 of 45 comments (clear)

  1. Finally, some competition by Btarlinian · · Score: 2, Insightful

    Intel has been losing so much market share in the server space recently. Maybe now they will be able to recover a little. Although, I'm not sure if this will compare to AMD's top offerings.

  2. Power efficiency is all good and nice but... by dc29A · · Score: 2, Insightful

    This CPU is crippled by a shared 667 mhz bus while the Opteron isn't.

    1. Re:Power efficiency is all good and nice but... by 2nd+Post! · · Score: 2, Insightful

      Yes, but isn't this also true of the other Core Duo solutions that happen to be equivalent in performance to Athlon/Opeteron CPUs?

      --

      GPL Deconstructed
    2. Re:Power efficiency is all good and nice but... by lsd · · Score: 4, Insightful

      Not exactly. On a single CPU system it makes little difference, but on 2 CPUs and up, the Opteron's NUMA architecture based on multiple memory controllers and high-speed point-to-point links between CPUs, each of which is quicker than the 667Mhz that these Core Duo-based Xeons will share for all memory access and cross-CPU traffic, is a huge win. As you can imagine, that win only increases when you move up to even larger systems.

    3. Re:Power efficiency is all good and nice but... by JollyFinn · · Score: 3, Informative

      While it might be "cripled" by FSB.
      Its faster than fastest opteron on perl and circuit layout part of spec int. And looses badly on chess ;)
      In overall its EQUAL to fastest dual core opteron on spec int.

      The fact remains that FSB is just ONE variable in huge nets of variables in performance equation.
      Using more cache means less memory accesses outside chip, using better prefetcher, helps memory access and soon, the off die memory accesses take such a small fraction of time, on MOST software that ondie memory controller vs FSB becomes non issue. [The percentage of improvement from ondie becomes less important than being flexible at new memory technologies on old sockets.]

      And memory accesses only take part of the time that must be improved other part is improving core, which part is often more important than improving the offchip memory accesses when there is enough cache. [depends on code].

      Take one thing that competitor can potentially do some what faster means nothing if you separate it from all the other aspects of CPU.

      --
      Emacs is good operating system, but it has one flaw: Its text editor could be better.
  3. A start, but no 64-bit? 667 Mhz front-side bus? by DonChron · · Score: 5, Insightful
    Intel's going to have to do a lot more than this to catch up to AMD in the server space. This is an improvement in power consumption, but they're still gated by the front-side-bus architecture which only gets more crowded as you add processors. And 32-bit only... they must really be feeling the heat (lack of heat?) from the Opteron to release a new 32-bit server processor when mature 64-bit OS's and applications are available. Even Microsoft x86-64 Windows and SQL Server products have been out for months, while x86-64 Linux and Linux apps have been out for years.

    It looks like they're desperate to show some progress...

  4. Re:Apple's new XServe by Wesley+Felter · · Score: 3, Interesting

    The inevitable Woodcrest-based Xserves should satisfy those people who only care about performance. Or they could just buy Opteron servers today.

  5. What's new? by Andy+Dodd · · Score: 2, Interesting

    The article specifies a TDP of 31W, a total of 2 MB cache (1M per core), 667 MHz FSB, and a clock speed of 2.0 GHz.

    How is this different from the Core Duo T2500? From the looks of it, there is none.

    --
    retrorocket.o not found, launch anyway?
    1. Re:What's new? by tomstdenis · · Score: 2, Informative

      Just a correction, if I'm not mistaken that's 2MB of L2 ... period. Not "per core". That means internally the bus between the cores and the cache is shared. Chances are there is some facilities to "prefer" a region of the cache [e.g. dual-ported] but as far as I've seen logically it's a 2MB cache both cores can access.

      Tom

      --
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    2. Re:What's new? by jdb8167 · · Score: 4, Informative

      Two things, SMP and a 34-bit address bus for up to 16GB of RAM.

  6. Re:Apple's new XServe by hpcanswers · · Score: 3, Interesting

    The whole reason people buy clusters instead of a specially built system like Cray's is for the cost. Running a large (hundreds of nodes) cluster costs upwards of tens of thousands a year for electricity and cooling. Energy efficiency is definitely warranted in this case. It's the same reason IBM's BlueGene employs 700 MHz PowerPC processors. http://en.wikipedia.org/wiki/Blue_Gene

  7. Dual processor configurations by NekoXP · · Score: 2, Informative

    Xeon LV supports SMP.. I think that is the only difference.

    Now it's been released I wonder if Apple are going to put out a PowerMac based on it..

    1. Re:Dual processor configurations by Jeff+DeMaagd · · Score: 2, Informative

      I wouldn't expect it to be PowerMac material. Code name Woodcrest is a better fit. It seems to clock a lot better (up to 3GHz, with a decent CPI to boot) with better cache (4MB per chip) and a better front side bus, up to 1333 MHz and support 64 bit instructions.

  8. Re:A start, but no 64-bit? 667 Mhz front-side bus? by gnuadam · · Score: 2, Interesting

    Alternately, apple put pressure for a chip that they can use to put in a new "core quad" (ie 2 of these) power mac to be announced 1 Apr? Timing's right ... (intel announces this 2 weeks before 1 Apr) ... Hmmmmm. At least this quad monster won't have to be water cooled.

    --
    You say :wq, I say ZZ. Why can't we all just get along?
  9. Re:A start, but no 64-bit? 667 Mhz front-side bus? by Burning1 · · Score: 2, Funny

    "Intel's going to have to do a lot more than this to catch up to AMD in the server space."

    Back in 2001 when I was just an AMD fanboy I would have made a mess in my pants upon hearing that.

  10. I don't mean to ponfificate, but by xactuary · · Score: 2, Funny
    Didn't Pope Zeon LV kiss the tarmac at Starfleet Academy?

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