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Intel Ships Core Duo-based Xeon
diegocgteleline.es writes "According to The Register, Intel has begun shipping a power-efficient dual-core "Xeon LV" and claims that it consumes no more than 31 W running at 2 Ghz, with a 667 Mhz frontside bus and sharing 2 MB of L2 between the two cores. The new chip has "four times the performance-per-Watt of its existing 2.8GHz LV Xeon CPU", not surprising given how slow and power inefficient those CPUs were. While this looks like a move to make AMD shares continue yesterday's tendency, it looks like Intel is starting to catching up?"
It looks like they're desperate to show some progress...
The inevitable Woodcrest-based Xserves should satisfy those people who only care about performance. Or they could just buy Opteron servers today.
The whole reason people buy clusters instead of a specially built system like Cray's is for the cost. Running a large (hundreds of nodes) cluster costs upwards of tens of thousands a year for electricity and cooling. Energy efficiency is definitely warranted in this case. It's the same reason IBM's BlueGene employs 700 MHz PowerPC processors. http://en.wikipedia.org/wiki/Blue_Gene
Not exactly. On a single CPU system it makes little difference, but on 2 CPUs and up, the Opteron's NUMA architecture based on multiple memory controllers and high-speed point-to-point links between CPUs, each of which is quicker than the 667Mhz that these Core Duo-based Xeons will share for all memory access and cross-CPU traffic, is a huge win. As you can imagine, that win only increases when you move up to even larger systems.
Two things, SMP and a 34-bit address bus for up to 16GB of RAM.
While it might be "cripled" by FSB. ;)
Its faster than fastest opteron on perl and circuit layout part of spec int. And looses badly on chess
In overall its EQUAL to fastest dual core opteron on spec int.
The fact remains that FSB is just ONE variable in huge nets of variables in performance equation.
Using more cache means less memory accesses outside chip, using better prefetcher, helps memory access and soon, the off die memory accesses take such a small fraction of time, on MOST software that ondie memory controller vs FSB becomes non issue. [The percentage of improvement from ondie becomes less important than being flexible at new memory technologies on old sockets.]
And memory accesses only take part of the time that must be improved other part is improving core, which part is often more important than improving the offchip memory accesses when there is enough cache. [depends on code].
Take one thing that competitor can potentially do some what faster means nothing if you separate it from all the other aspects of CPU.
Emacs is good operating system, but it has one flaw: Its text editor could be better.