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48 Core Vega 2 in the Making
TobyKY76 writes to tell us The Inquirer is reporting that upstart Azul Systems is planning to integrate 48 cores on their next generation chip. From the article: "The first-generation Vega processor it designed has 24 cores but the firm expects to double that level of integration in systems generally available next year with the Vega 2, built on TSMC's 90nm process and squeezing in 812 million transistors. The progress means that Azul's Compute Appliances will offer up to 768-way symmetric multiprocessing."
I know of a certain project that's working to put over a million cores into a system (160 into a single chip), and it should be finished and available off-the-shelf within a year or so.
To make laws that man cannot, and will not obey, serves to bring all law into contempt.
--E.C. Stanton
"Each 64-bit Cyclops64 chip (processor) will run at 500 megahertz and contain 80 cores." While it may have two threads per core, that is not what you claimed. You stated "...that's working to put over a million cores into a system (160 into a single chip)". 160 threads per chip, yes, but not 160 cores.
The number of transistors can go up for a variety of reasons. Chief among them is designs that utilize complex performance enhancements. To name a few:
The secondary source of transistor usage is coprocessors like Floating Point Units and SIMD Units.
The latest craze in processor design is to simplify the microprocessor back down to the most basic level. From there, the processors are ramped up through shear numbers of parallel pipelines (i.e. threads) and cores as opposed to ramping up the individual CPU horsepower. These multi-core chips typically share coprocessors among a pipelines or cores, and may even have entire cores dedictated to specific tasks like SIMD. As a result, a properly designed program will be able to execute within a very short period of time, thanks to the parallel nature of the multi-core architecture.
Now the only problem is in finding these "properly written programs".
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The box is a flat SMP - if a core misses in L2 it's the same cost to any piece of memory (or remote L2).
The cores are our own design, not MIPs, not ARM, etc. Simple, short in-order pipeline, decent caches (not huge) caches.
Power consumption is very low compared to the equivalent stack of P4 blades or other main-frame solution.
The first-gen box (368 cores) is about 2700 watts in an 11U rack mount.
Next-gen box isn't much bigger, nor draws very much more power (a little more of both I belive).