Intel's 3D Transistors One Step Closer to Reality

An anonymous reader writes "Reducing power consumption is the name of the game in today's semiconductors and Intel today described its tri-gate transistor technology as one of the key technologies that could free the company from the trap of thinner gate insulators and increasing current leakage. Tri-gate (three gates instead of only one) could reduce the power consumption of transistors by 35% right now and drops off-voltage - one of the main sources of current leakage - by 50%. These results are the good news. The bad news is that tri-gate won't be available until 2009."

Comments

Looks Like FinFET To Me

[Anonymous Coward]

Is there a difference, or is Intel just calling it by a different name? (FinFET diagram: http://www.future-fab.com/assets/images/FF19_wp_pa rton_fig1.gif)

Not really a drawback

[overshoot]

Pretty cool, but that should come with a 3x increase in the gate's capacitance, shouldn't it? and fighting capacitance is one of the major struggles of increased speed, right? People doing very low-power stuff should love this. People doing high-speed design, maybe not so much.

Not really a problem. The transconductance of a transistor is actually proportional to the charge induced in the channel, which in turn is proportional to the gate voltage (limited) and the capacitance. In other words, you aren't going to get more gain without also getting more capacitance. In other words, for a given gain the capacitance is the same, but the leakage is less. [1]

The other reason this isn't a problem for low power is that interconnect capacitance is much greater than gate capacitance for practical circuits.

[1] Size isn't much affected, because so many other features are much larger than the channel. Contacts and required spacings, for instance.

Re:Unclear what the problem is.

[overshoot]

Tunnels sound very interesting. Leakage presumably has many causes, but would boil down to electrons leaving the desired path and going elsewhere. There MAY be ways of replacing the interconnects (which are usually just regular conductors) with superconductors, as superconductors should leak a lot less. (Resistance is a function of leakage, and superconductors have zero resistance.) This won't fix links on the silicon itself, but any improvement would be a good thing.

• Leakage in this context is actually either:
  • Current that flows in the channel of an OFF transistor (this helps with that) or,
  • Current that flows through the gate dielectric (this doesn't help, you need high-K dielectrics for that)
• Superconductors don't leak, dielectrics do. You may be thinking of losses.
• Resistance isn't a function of leakage. Don't know where you got that one.
• Actually, the described improvement will "fix links (sic) on the silicon itself"

Re:Intel cooler than AMD!

[Spy der Mann]

And what is AMD doing in R&D lately?

*AHEM*

AMD readies multigate transistor for 45-nm node (Sept 18, 2003).

AUSTIN, Texas -- Advanced Micro Devices researchers have developed a low aspect ratio Finfet-like transistor the company may begin producing as early as 2007 at the 45-nm node.

Zoran Krivokapic, the lead researcher on the multigate project, based at the company's technology research group in Sunnyvale, Calif., reported that the transistor switching speed -- expressed as CV/I, a measure of capacitance, voltage and current -- was 0.26 picoseconds for the NMOS devices and 0.45 ps for the PMOS transistors. AMD said those are the fastest transistors reported to date for 20-nm gate length structures.

The multigate device was introduced by AMD at the International Conference on Solid State Devices and Materials (SSDM) in Tokyo on Thursday (Sept. 18).

The gate surrounds a vertical channel, rather than the planer structure which stacks the channel, gate oxide and electrodes between the source and drain. The AMD structure has a lower aspect ratio than conventional FinFETs, which eases the burden on the lithographic tool and its depth of field.

AMD combined several process technology advances in the multigate structure. It used fully silicided (FUSI) metal gates, instead of electrodes made of polysilicon. Rather than depositing the nickel material, the AMD approach uses a silicidation process to gradually replace polysilicon with nickel silicide to form the metal gate electrodes.

Also, AMD employed fully depleted SOI (silicon on insulator). The fully depleted SOI combined with the metal gate creates a strain on the silicon in the channel, delivering higher-mobility electrons and holes.

Craig Sander, AMD vice president of process technology, said the multigate transistor will allow AMD to maintain roughly 20- percent per annum improvements in performance that has been standard for the semiconductor industry.

The multigate device "demonstrates 50 percent better performance than other multigate devices" discussed in the literature thus far, Sander said.

The stage delay, for example, exceeds the specifications set out by the 2003 International Technology Roadmap for Semiconductors for devices coming to market in the 2009 timeframe.

Sander said the multigate transistor delivers higher performance while keeping additional process complexity to a minimum. He said the multigate structure "is a prime candidate for the 45-nm node," expected to enter manufacturing as early as 2007.

AMD's multigate transistor is one of several recent announcements indicating that the vertical structures could replace planar CMOS transistors in high-performance devices much earlier than expected a few years ago. Intel Corp. executives, speaking at the Intel Developer Forum this week, indicated they expect some form of a multigate transistor to be introduced at the 45-nm node. Motorola, Taiwan Semiconductor Manufacturing Co. Ltd. and others also are pursuing the technology.

Happy now? :)

Re:Unclear what the problem is.

[Agripa]

The additional grids added to tubes serve a different purpose then the "triple gate" Intel is testing. Tetrodes add a screen grid which acts to lower Miller capacitance (the capacitance between the control grid and plate multiplied by the voltage gain) as well as lowering space charge. Both bipolar transistors and field effect transisters suffer from Miller capacitance and in the case of dual gate MOSFETs the second gate can be used in a similar way or a cascode configuration can be used. The third grid in a pentode suppresses secondary emmision from the plate which raises the gain.

Re:3D

[Anonymous Coward]

No, it doesn't.

Both FinFETs and Trigates are built on an SOI substrate ( silicon -oxide -silicon) whereas planar MOSFETs are built 'into' a silicon substrate; their channel is in the substrate, whereas the FinFETs' and trigates' is in the top layer of silicon. Trigate FETs are 3-D because the Si channel is 3-D with the gate wrapped around it on the top, front and back. Because it is 3D, it does not suffer from the short channel effects that planar MOSFETs do (due to an intrinsic channel ie no doping required, so no impurity scattering which translates into resistance) -- this makes them able to be scaled smaller, faster and consume less power -- threshold voltage not dependant on doping (as much). . .

AMD is researching FinFETS, which IMHO is a better route because eventually trigates will become FinFETs as they get smaller. For a trigate, all three gates are roughly the same size, but in FinFETs the front and back gates are much larger, so trigates have a square cross section and finFETs have a rectangular. Also, FinFETs are basically dual gate devices since the top gate is so small, it is negligable (and the oxide is deeper, thus less E field).

Big benefit to both is the channel is intrinisic(faster, less resistance) and are compatible with current MOSFET fab techniques, though the trigate is more attainable now just because the top view of the channel is thicker, so easier for fab equipment to make consistently. As you get smaller, the fab equipment must be much more precise.