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China to Make $125 PCs
TechFreep writes "A Chinese computer company hopes to sell low-cost PCs to schools and government agencies, but allegations of ripped-off processor designs might slow the effort. From the article:
'Chinese-based ZhongKe Menglan Electronics Technology Co. will produce several thousand low-cost PCs to distribute to schools and local governments. The PCs, which will initially sell for $150 to $175, will run on Linux and include 256Mb of RAM, a 40 or 60GB hard drive, and a Godson-2 CPU clocked between 800Mhz and 1Ghz. If initial sales of the product are successful ZhongKe will begin mass production of the units for sale at around 125 US dollars.
However, the Godson-2 CPU included in the PCs has come under scrutiny of late. BLX IC Design Corp., producer of the Godson-2, produced its first working prototype in 2005. The chip clocked at 500Mhz, and BLX at the time claimed the Godson's performance rivaled that of higher-clocked Pentium III CPUs. However, the chip's architecture has gotten attention around the industry for its similarities to the MIPS chip from MIPS Technologies Inc. According to market research group In-Stat, the Godson-2 is about 95 percent compatible with the MIPS R10000, which was introduced in 1995.'"
The MIPS architecture is a popular one with people who implement their own cores. In fact, it is rather common for computer science/engineering students to implement their own using FPGAs, based on the commonly used Computer Architecture by Hennessy and Patterson. The architecture is extremely simple, straightforward, and easy to implement.
I believe you can implemented a near complete MIPS R3000 core with only minor differences and avoid any patent issues (as long as you don't call it a MIPS). Some of the ops on the newer cores are still encumbered and cannot be implemented without paying money to MIPS Technologies. I've worked with a couple of MIPS clones, some by American companies, and there is nothing illegal about them. In fact, it would be far more surprising if the Chinese companies wasted the time creating their own architecture instead of basing it on a proven one.
It's worth noting that the patent most likely to be stepped on in dealing with MIPS is US patent 4,814,976, which covers the unaligned load/store instructions lwl, lwr, swl and swr. This patent expires 2006-12-26, which won't be long now. Google for "Lexra" "MIPS" and "Patent" for details of the various spats over the patent.
Apparently some of the more recent extensions fall under other patents, but the basic archetecture will be entirely unencumbered after this one expires. And as a Computer Enginering student I can tell you as ISAs go it's far and away the easiest useful one to impliment.
But you may be one of the fortunates who go to school where Hennessy is president, so you may have learned MIPS there =P
I take it you mean Stanford. I went to UCLA, but many people I've met from different schools in the US have used the same architecture book. I'm talking about computer architecture, not just assembly language. The complexity of the x86 processors is far too great to teach them to undergrads. However, in about a hundred hours of work, one lab partner and I were able to construct a working MIPS-architecture CPU (on a Xilinx FPGA) starting with nothing but gates, flipflops, and other basic elements.
Now, since you know x86 assembly, let me teach you MIPS assembly in one minute:
32 registers, r0-r31. r0 is hardcoded to zero. jal/bal (jump/branch and link) push the PC to r31. otherwise, all registers are equal.
li rD VAL ; load to register rD (destination) immediate value VAL
lw rD rS ; load word at address stored in rS (source) to
add/sub/... rD rA rB ; perform op on registers A and B, store to register D
sw rD rS ; store word at rD to address in rS
You'll be doing a lot of load/stores. The instruction after a branch statement gets executed even if the branch is called. The rest is just details (extend to half-words and bytes at your convenience). There are no index registers, no flags, no predicates, nothing. Congratulations, you are now qualified to program a MIPS processor.
No, often you can find an instruction to put after the branch. Sparc is the same. It's called the "branch delay slot", and it's a way of reducing the pipeline flush penalty.